ST16C554DIJ68-F Exar Corporation, ST16C554DIJ68-F Datasheet - Page 13

• Manufacturer Part Number: ST16C554DIJ68-F
• Description: IC UART FIFO 16B QUAD 68PLCC
• Manufacturer: Exar Corporation
• Type: Quad UART with 16-byte FIFOsr

Specifications of ST16C554DIJ68-F

• Number Of Channels: 4, QUART
• Package / Case: 68-LCC (J-Lead)
• Features: *
• Fifo's: 16 Byte
• Protocol: RS232
• Voltage - Supply: 2.97 V ~ 5.5 V
• With Auto Flow Control: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Data Rate: 1.5 Mbps
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.97 V
• Supply Current: 6 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V, 5 V
• No. Of Channels: 4
• Supply Voltage Range: 2.97V To 5.5V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: PLCC
• No. Of Pins: 68
• Filter Terminals: SMD
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 1016-1267-5

REV. 4.0.1
The Receive Holding Register is an 8-bit register that holds a receive data byte from the Receive Shift
Register. It provides the receive data interface to the host processor. The RHR register is part of the receive
FIFO of 16 bytes by 11-bit wide, the 3 extra bits are for the 3 error tags to be reported in LSR register. When
the FIFO is enabled by FCR bit-0, the RHR contains the first data character received by the FIFO. After the
RHR is read, the next character byte is loaded into the RHR and the errors associated with the current data
byte are immediately updated in the LSR bits 2-4.
F
F
2.10.1
IGURE
IGURE
R eceive D ata
Byte and Errors
8. R
9. R
16 bytes by 11-bit w ide
Receive Holding Register (RHR) - Read-Only
16X C lock
ECEIVER
ECEIVER
FIFO
and Errors
16X Clock
Data Byte
Receive
O
O
PERATION IN NON
PERATION IN
R eceive D ata Shift
R egister (R SR )
FIFO
D ata FIFO
R eceive
LSR bits
Tags in
R eceive
Error
D ata
4:2
-FIFO M
Receive Data Shift
Register (RSR)
Holding Register
Receive Data
ODE
V alidation
D ata falls to
D ata fills to
D ata Bit
Trigger=8
(RHR)
FIFO
14
E xam ple
4
13
: - R X FIFO trigger level selected at 8 bytes
2.97V TO 5.5V QUAD UART WITH 16-BYTE FIFO
Asking for sending data w hen data falls below the flow
Asking for stopping data w hen data fills above the flow
control trigger level to restart rem ote transm itter.
control trigger level to suspend rem ote transm itter.
Validation
R H R Interrupt (IS R bit-2) program m ed for
(See N ote Below )
desired FIFO trigger level.
FIFO is Enabled by FC R bit-0=1
Data Bit
RHR Interrupt (ISR bit-2)
Receive Data Characters
R eceive D ata C haracters
ST16C554/554D
RXFIFO1
R XFIFO 1