ST16C554DIJ68-F Exar Corporation, ST16C554DIJ68-F Datasheet - Page 16

• Manufacturer Part Number: ST16C554DIJ68-F
• Description: IC UART FIFO 16B QUAD 68PLCC
• Manufacturer: Exar Corporation
• Type: Quad UART with 16-byte FIFOsr

Specifications of ST16C554DIJ68-F

• Number Of Channels: 4, QUART
• Package / Case: 68-LCC (J-Lead)
• Features: *
• Fifo's: 16 Byte
• Protocol: RS232
• Voltage - Supply: 2.97 V ~ 5.5 V
• With Auto Flow Control: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Data Rate: 1.5 Mbps
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.97 V
• Supply Current: 6 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V, 5 V
• No. Of Channels: 4
• Supply Voltage Range: 2.97V To 5.5V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: PLCC
• No. Of Pins: 68
• Filter Terminals: SMD
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 1016-1267-5

ST16C554/554D
2.97V TO 5.5V QUAD UART WITH 16-BYTE FIFO
SEE”RECEIVER” ON PAGE 12.
SEE”TRANSMITTER” ON PAGE 11.
The Interrupt Enable Register (IER) masks the interrupts from receive data ready, transmit empty, line status
and modem status registers. These interrupts are reported in the Interrupt Status Register (ISR).
4.0 INTERNAL REGISTER DESCRIPTIONS
4.1
4.2
4.3
A
A2-A0
DDRESS
0 0 0
0 0 0
0 0 1
0 1 0
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
0 0 0
0 0 1
Receive Holding Register (RHR) - Read- Only
Transmit Holding Register (THR) - Write-Only
Interrupt Enable Register (IER) - Read/Write
N
MCR
RHR
MSR
DLM
THR
FCR
LCR
SPR
R
LSR
DLL
IER
ISR
AME
EG
RD/WR
RD/WR Divisor
RD/WR
RD/WR
RD/WR
RD/WR
RD/WR
RD/WR
R
W
WR
WR
RD
RD
EAD
RITE
/
RX FIFO
Enabled
Trigger
Enable
Global
FIFOs
T
B
FIFO
Error
Input
Bit-7
Bit-7
Bit-7
Bit-7
Bit-7
CD#
RX
ABLE
IT
0
0
-7
8: INTERNAL REGISTERS DESCRIPTION.
RX FIFO
Enabled
Trigger
Set TX
THR &
Empty
FIFOs
Break
B
Input
Bit-6
Bit-6
TSR
Bit-6
Bit-6
Bit-6
RI#
IT
0
0
-6
16C550 Compatible Registers
Baud Rate Generator Divisor
Empty
Parity
DSR#
B
Input
Bit-5
Bit-5
THR
Bit-5
Bit-5
Bit-5
Set
IT
0
0
0
0
-5
16
RX Break
Lopback
Internal
Enable
Parity
CTS#
B
Even
Input
Bit-4
Bit-4
Bit-4
Bit-4
Bit-4
IT
0
0
0
-4
Framing
Modem
Source
(OP2#)
Enable
Enable
Enable
Enable
Output
Mode
Parity
B
Delta
DMA
Error
Bit-3
Bit-3
Bit-3
Bit-3
Bit-3
Bit-3
Stat.
CD#
INT
INT
Int.
RX
IT
-3
RX Line
(OP1#)
Enable
Source
Reset
Parity
B
FIFO
Rsvd
Error
Delta
Bit-2
Bit-2
Stat.
Bit-2
Stop
Bit-2
Bit-2
Bit-2
INT
Bits
RI#
Int.
TX
RX
IT
-2
Control
Enable
Source
Length
Output
Empty
DSR#
Reset
RTS#
Over-
Word
B
FIFO
Error
Delta
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
INT
run
TX
RX
RX
Int
IT
-1
Control
Enable
Source
Enable
Length
Output
FIFOs
Ready
DTR#
CTS#
Word
B
Delta
Data
Data
Bit-0
Bit-0
Bit-0
Bit-0
Bit-0
Bit-0
Bit-0
INT
RX
Int.
RX
IT
-0
LCR[7] = 0
LCR[7] = 0
LCR≠0xBF
C
LCR[7]=1
REV. 4.0.1
OMMENT