ST16C554DIJ68-F Exar Corporation, ST16C554DIJ68-F Datasheet - Page 6

• Manufacturer Part Number: ST16C554DIJ68-F
• Description: IC UART FIFO 16B QUAD 68PLCC
• Manufacturer: Exar Corporation
• Type: Quad UART with 16-byte FIFOsr

Specifications of ST16C554DIJ68-F

• Number Of Channels: 4, QUART
• Package / Case: 68-LCC (J-Lead)
• Features: *
• Fifo's: 16 Byte
• Protocol: RS232
• Voltage - Supply: 2.97 V ~ 5.5 V
• With Auto Flow Control: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Data Rate: 1.5 Mbps
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.97 V
• Supply Current: 6 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V, 5 V
• No. Of Channels: 4
• Supply Voltage Range: 2.97V To 5.5V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: PLCC
• No. Of Pins: 68
• Filter Terminals: SMD
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 1016-1267-5

ST16C554/554D
2.97V TO 5.5V QUAD UART WITH 16-BYTE FIFO
REV. 4.0.1
1.0 PRODUCT DESCRIPTION
The ST16C554 (554) integrates the functions of 4 enhanced 16C550 Universal Asynchrounous Receiver and
Transmitter (UART). Each UART is independently controlled and has its own set of device configuration
registers. The configuration registers set is 16550 UART compatible for control, status and data transfer.
Additionally, each UART channel has 16 bytes of transmit and receive FIFOs, programmable baud rate
generator and data rate up to 1.5 Mbps at 5V. The ST16C554 can operate from 2.97 to 5.5 volts. The 554 is
fabricated with an advanced CMOS process.
Enhanced FIFO
The 554 QUART provides a solution that supports 16 bytes of transmit and receive FIFO memory, instead of
one byte in the ST16C454. The 554 is designed to work with high performance data communication systems,
that require fast data processing time. Increased performance is realized in the 554 by the larger transmit and
receive FIFOs and Receiver FIFO trigger level control. This allows the external processor to handle more
networking tasks within a given time. This increases the service interval giving the external CPU additional time
for other applications and reducing the overall UART interrupt servicing time.
Data Bus Interface, Intel or Motorola Type
The 554 provides a single host interface for all 4 UARTs and supports Intel or Motorola microprocessor (CPU)
data bus interface. The Intel bus compatible interface allows direct interconnect to Intel compatible type of
CPUs using IOR#, IOW# and CSA#, CSB#, CSC# and CSD# inputs for data bus operation. The Motorola bus
compatible interface instead uses the R/W#, CS#, A3 and A4 signals for data bus transactions. Few data bus
interface signals change their functions depending on user’s selection, see pin description for details. The Intel
and Motorola bus interface selection is made through the 16/68# (pin 31 of the PLCC package).
Data Rate
The 554 is capable of operation up to 1.5 Mbps at 5V. The device can operate at 5V with a crystal or external
clock of up to 24 MHz. With a typical crystal of 14.7456 MHz and through a software option, the user can set
the sampling rate for data rates of up to 921.6 Kbps.
Enhanced Features
The rich feature set of the 554 is available through the internal registers. Selectable receive FIFO trigger levels,
programmable baud rates, infrared encoder/decoder interface and modem interface controls are all standard
features. In the 16 mode INTSEL and MCR bit-3 can be configured to provide a software controlled or
continuous interrupt capability. For backward compatibility to the ST16C554, the 64-pin LQFP does not have
the INTSEL pin. Instead, two different LQFP packages are offered. The ST16C554DIV operates in the
continuous interrupt enable mode by internally bonding INTSEL to VCC. The ST16C554IV operates in
conjunction with MCR bit-3 by internally bonding INTSEL to GND.
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