LFE2-20E-5FN484C Lattice, LFE2-20E-5FN484C Datasheet - Page 82

• Manufacturer Part Number: LFE2-20E-5FN484C
• Description: FPGA - Field Programmable Gate Array 21K LUTs 331 I/O DSP 1.2V -5
• Manufacturer: Lattice
• Series: LatticeECP2r

Specifications of LFE2-20E-5FN484C

• Number Of Macrocells: 21000
• Number Of Programmable I/os: 331
• Data Ram Size: 282624
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Package / Case: FPBGA-484
• No. Of Logic Blocks: 21000
• No. Of Macrocells: 10500
• No. Of Speed Grades: 5
• Total Ram Bits: 276Kbit
• No. Of I/o's: 331
• Clock Management: DLL, PLL
• I/o Supply Voltage: 3.465V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Timing Diagrams
Figure 3-9. Read/Write Mode (Normal)
Note: Input data and address are registered at the positive edge of the clock and output data appears after the positive edge of the clock.
Figure 3-10. Read/Write Mode with Input and Output Registers
CLKA
DOA (Regs)
WEA
DOA
CSA
ADA
DIA
CLKA
WEA
ADA
CSA
DIA
t
SU
A0
D0
t
t
H
SU
A0
D0
t
H
Mem(n) data from previous read
A1
D1
A1
D1
3-30
output is only updated during a read cycle
A0
t
A0
CO_EBR
t
COO_EBR
DC and Switching Characteristics
LatticeECP2/M Family Data Sheet
D0
A1
A1
t
CO_EBR
D0
D1
A0
A0
t
CO_EBR
t
COO_EBR
D1
D0