LFE2-20E-5FN484C Lattice, LFE2-20E-5FN484C Datasheet - Page 99

• Manufacturer Part Number: LFE2-20E-5FN484C
• Description: FPGA - Field Programmable Gate Array 21K LUTs 331 I/O DSP 1.2V -5
• Manufacturer: Lattice
• Series: LatticeECP2r

Specifications of LFE2-20E-5FN484C

• Number Of Macrocells: 21000
• Number Of Programmable I/os: 331
• Data Ram Size: 282624
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Package / Case: FPBGA-484
• No. Of Logic Blocks: 21000
• No. Of Macrocells: 10500
• No. Of Speed Grades: 5
• Total Ram Bits: 276Kbit
• No. Of I/o's: 331
• Clock Management: DLL, PLL
• I/o Supply Voltage: 3.465V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

LatticeECP2/M sysCONFIG Port Timing Specifications (Continued)
Lattice Semiconductor
Figure 3-14. sysCONFIG Parallel Port Read Cycle
t
t
1. Re-toggling the PROGRAMN pin is not permitted until the INITN pin is high. Avoid consecutive toggling of the PROGRAMN.
2. For SED (Soft Error Detect), the SEDCLKIN operating frequency must be at least 20MHz. SEDCLKIN is derived from Master Clock Fre-
Master Clock Frequency
Duty Cycle
SUSPI
HSPI
quency that has a +/-30% variation..
Parameter
Parameter
WRITEN
SOSPI Data Setup Time Before CCLK
SOSPI Data Hold Time After CCLK
CCLK
CS1N
BUSY
D[0:7]
*n = last byte of read cycle.
CSN
Selected value - 30%
Over Recommended Operating Conditions
Min.
40
t
t
Description
SUCS
SUWD
Byte 0
t
BSCL
3-47
Byte 1
t
CORD
Selected value + 30%
Max.
t
60
DCB
DC and Switching Characteristics
LatticeECP2/M Family Data Sheet
t
Byte 2
BSCYC
t
BSCH
Byte n*
Min.
t
t
7
2
HCS
HWD
Units
MHz
Max.
%
—
—
Units
ns
ns