LFE2-20E-5FN484C Lattice, LFE2-20E-5FN484C Datasheet - Page 88

• Manufacturer Part Number: LFE2-20E-5FN484C
• Description: FPGA - Field Programmable Gate Array 21K LUTs 331 I/O DSP 1.2V -5
• Manufacturer: Lattice
• Series: LatticeECP2r

Specifications of LFE2-20E-5FN484C

• Number Of Macrocells: 21000
• Number Of Programmable I/os: 331
• Data Ram Size: 282624
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Package / Case: FPBGA-484
• No. Of Logic Blocks: 21000
• No. Of Macrocells: 10500
• No. Of Speed Grades: 5
• Total Ram Bits: 276Kbit
• No. Of I/o's: 331
• Clock Management: DLL, PLL
• I/o Supply Voltage: 3.465V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
sysCLOCK SPLL Timing
f
f
f
f
f
AC Characteristics
t
t
t
t
t
t
t
t
t
t
t
1. Jitter sample is taken over 10,000 samples of the primary PLL output with clean reference clock and no additional I/O pins toggling.
2. Output clock is valid after t
3. Using LVDS output buffers.
4. Phase accuracy of CLKOS compared to CLKOP.
5. Value of external capacitor: 5.6 nF ±20%, NPO dielectric, ceramic chip capacitor, 1206 or smaller package, connected to PLLCAP pin.
6. f
Parameter
IN
OUT
OUT2
VCO
PFD
DT
PH
OPJIT
SK
W
LOCK
IPJIT
FBKDLY
HI
LO
RST
4
OUT
2
1
(max) = f
Input Clock Frequency (CLKI, CLKFB)
Output Clock Frequency (CLKOP, CLKOS)
K-Divider Output Frequency (CLKOK)
PLL VCO Frequency
Phase Detector Input Frequency
Output Clock Duty Cycle
Output Phase Accuracy
Output Clock Period Jitter
Input Clock to Output Clock Skew
Output Clock Pulse Width
PLL Lock-in Time
Input Clock Period Jitter
External Feedback Delay
Input Clock High Time
Input Clock Low Time
RST Pulse Width (RESETM/RESETK)
Reset Signal Pulse Width (CNTRST)
IN
* 10 for f
IN
LOCK
< 5MHz.
Description
for PLL reset and dynamic delay adjustment.
Over Recommended Operating Conditions
Without external capacitor
With external capacitor
Without external capacitor
With external capacitor
Without external capacitor
With external capacitor
Without external capacitor
With external capacitor
Default Duty Cycle Selected
f
50  f
f
Divider Ratio = Integer
At 90% or 10%
Without external capacitor
With external capacitor
90% to 90%
10% to 10%
Without external capacitor
With external capacitor
OUT
OUT
3-36
 100 MHz
< 50 MHz
OUT
< 100 MHz
Conditions
DC and Switching Characteristics
LatticeECP2/M Family Data Sheet
5, 6
5
5
6
5
5
3
0.258
0.039
Min.
640
500
0.5
0.5
33
33
33
45
15
20
—
—
—
—
—
—
—
—
—
2
5
2
1
Typ.
50
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
±0.05
0.025
Max.
1280
±125
±250
±200
0.04
420
420
420
210
420
150
500
50
25
50
55
—
10
—
—
—
—
—
Units
UIPP
UIPP
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
ps
ps
ns
µs
µs
ps
ns
ns
ns
ns
ns
µs
%
UI