LFXP3C-3TN144I Lattice, LFXP3C-3TN144I Datasheet - Page 166

• Manufacturer Part Number: LFXP3C-3TN144I
• Description: FPGA - Field Programmable Gate Array 3.1K LUTs 100 I/O 1.8/2.5/3.3V IND
• Manufacturer: Lattice

Specifications of LFXP3C-3TN144I

• Number Of Programmable I/os: 100
• Data Ram Size: 55296
• Supply Voltage (max): 3.465 V
• Maximum Operating Temperature: + 100 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.71 V
• Package / Case: TQFP-144
• Package: 144TQFP
• Family Name: LatticeXP
• Device Logic Units: 3000
• Maximum Internal Frequency: 320 MHz
• Typical Operating Supply Voltage: 1.8|2.5|3.3 V
• Maximum Number Of User I/os: 100
• Ram Bits: 55296
• Re-programmability Support: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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October 2006
Introduction
This technical note discusses memory usage in the LatticeEC™, LatticeECP™ and LatticeXP™ device families. It
is intended to be used as a guide for integrating the EBR and PFU based memories for these device families using
the ispLEVER
The architecture of the LatticeECP/EC and LatticeXP devices provides a large amount of resources for memory
intensive applications. The sysMEM™ Embedded Block RAM (EBR) complements its distributed PFU-based mem-
ory. Single-Port RAM, Dual-Port RAM, Pseudo Dual-Port RAM and ROM memories can be constructed using the
EBR. LUTs and PFU can implement Distributed Single-Port RAM, Dual-Port RAM and ROM. The internal logic of
the device can be used to configure the memory elements as FIFO and other storage types.
The capabilities of the EBR Block RAM and PFU RAM are referred to as primitives and described later in this doc-
ument. Designers can generate the memory primitives using the IPexpress™ tool in the ispLEVER software. The
IPexpress GUI allows users to specify the memory type and size required. IPexpress takes this specification and
constructs a netlist to implement the desired memory by using one or more of the memory primitives.
The remainder of this document discusses how to utilize IPexpress, memory modules and memory primitives.
Memories in LatticeECP/EC and LatticeXP Devices
The LatticeECP/EC and LatticeXP architectures contain an array of logic blocks called PFUs or PFFs surrounded
by Programmable I/O Cells (PICs). Interspersed between the rows of logic blocks are rows of sysMEM Embedded
Block RAM (EBR) as shown in Figures 9-1, 9-2 and 9-3.
The PFU contains the building blocks for logic, and Distributed RAM and ROM. The PFF provides the logic building
blocks without the distributed RAM
This document describes the memory usage and implementation for both embedded memory blocks (EBR) and
distributed RAM of the PFU. Refer to the device data sheet for details on the hardware implementation of the EBR
and Distributed RAM.
The logic blocks are arranged in a two-dimensional grid with rows and columns as shown in the figures below. The
physical location of the EBR and Distributed RAM follows the row and column designation. The Distributed RAM,
since it is part of the PFU resource, follows the PFU/PFF row and column designation. The EBR occupies two col-
umns per block to account for the wider port interface.
®
design tool.
LatticeECP/EC and LatticeXP Devices
9-1
Memory Usage Guide for
Technical Note TN1051
tn1051_01.8