LFXP3C-3TN144I Lattice, LFXP3C-3TN144I Datasheet - Page 241

• Manufacturer Part Number: LFXP3C-3TN144I
• Description: FPGA - Field Programmable Gate Array 3.1K LUTs 100 I/O 1.8/2.5/3.3V IND
• Manufacturer: Lattice

Specifications of LFXP3C-3TN144I

• Number Of Programmable I/os: 100
• Data Ram Size: 55296
• Supply Voltage (max): 3.465 V
• Maximum Operating Temperature: + 100 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.71 V
• Package / Case: TQFP-144
• Package: 144TQFP
• Family Name: LatticeXP
• Device Logic Units: 3000
• Maximum Internal Frequency: 320 MHz
• Typical Operating Supply Voltage: 1.8|2.5|3.3 V
• Maximum Number Of User I/os: 100
• Ram Bits: 55296
• Re-programmability Support: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
POL(ddrclkpol_sig),
POL(ddrclkpol_sig),
POL(ddrclkpol_sig),
POL(ddrclkpol_sig),
POL(ddrclkpol_sig),
POL(ddrclkpol_sig),
POL(ddrclkpol_sig),
-
-
//----------------------------------------------------------------------------------------
//----TRISTATE Instantiations-------------------------------------------------------------
// DDR Trisate for data, DQ
ODDRXB T0 (.DA(datatri_p[0]), .DB(datatri_n[0]), .LSR(reset), .CLK(~clk), .Q(tridata[0]));
ODDRXB T1 (.DA(datatri_p[1]), .DB(datatri_n[1]), .LSR(reset), .CLK(~clk), .Q(tridata[1]));
ODDRXB T2 (.DA(datatri_p[2]), .DB(datatri_n[2]), .LSR(reset), .CLK(~clk), .Q(tridata[2]));
ODDRXB T3 (.DA(datatri_p[3]), .DB(datatri_n[3]), .LSR(reset), .CLK(~clk), .Q(tridata[3]));
ODDRXB T4 (.DA(datatri_p[4]), .DB(datatri_n[4]), .LSR(reset), .CLK(~clk), .Q(tridata[4]));
ODDRXB T5 (.DA(datatri_p[5]), .DB(datatri_n[5]), .LSR(reset), .CLK(~clk), .Q(tridata[5]));
ODDRXB T6 (.DA(datatri_p[6]), .DB(datatri_n[6]), .LSR(reset), .CLK(~clk), .Q(tridata[6]));
ODDRXB T7 (.DA(datatri_p[7]), .DB(datatri_n[7]), .LSR(reset), .CLK(~clk), .Q(tridata[7]));
// DDR Trisate for strobe, DQS
ODDRXB T8 (.DA(dqstri_p), .DB(dqstri_n), .LSR(reset), .CLK(clk90), .Q(tridqs));
//-----------------------------------------------------------------------------------------
//-----------DQ output---------------------------------------------------------------------
ODDRXB O0 (.DA(dataout_p[0]), .DB(dataout_n[0]), .LSR(reset), .CLK(~clk), .Q(ddrout[0]));
ODDRXB O1 (.DA(dataout_p[1]), .DB(dataout_n[1]), .LSR(reset), .CLK(~clk), .Q(ddrout[1]));
ODDRXB O2 (.DA(dataout_p[2]), .DB(dataout_n[2]), .LSR(reset), .CLK(~clk), .Q(ddrout[2]));
ODDRXB O3 (.DA(dataout_p[3]), .DB(dataout_n[3]), .LSR(reset), .CLK(~clk), .Q(ddrout[3]));
ODDRXB O4 (.DA(dataout_p[4]), .DB(dataout_n[4]), .LSR(reset), .CLK(~clk), .Q(ddrout[4]));
ODDRXB O5 (.DA(dataout_p[5]), .DB(dataout_n[5]), .LSR(reset), .CLK(~clk), .Q(ddrout[5]));
ODDRXB O6 (.DA(dataout_p[6]), .DB(dataout_n[6]), .LSR(reset), .CLK(~clk), .Q(ddrout[6]));
ODDRXB O7 (.DA(dataout_p[7]), .DB(dataout_n[7]), .LSR(reset), .CLK(~clk), .Q(ddrout[7]));
IDDRXB
IDDRXB
IDDRXB
IDDRXB
IDDRXB
IDDRXB
IDDRXB
UL1
UL2
UL3
UL4
UL5
UL6
UL7
.LSR(reset), .QA(datain_p[1]), .QB(datain_n[1]));
.LSR(reset), .QA(datain_p[2]), .QB(datain_n[2]));
.LSR(reset), .QA(datain_p[3]), .QB(datain_n[3]));
.LSR(reset), .QA(datain_p[4]), .QB(datain_n[4]));
.LSR(reset), .QA(datain_p[5]), .QB(datain_n[5]));
.LSR(reset), .QA(datain_p[6]), .QB(datain_n[6]));
.LSR(reset), .QA(datain_p[7]), .QB(datain_n[7]));
(.D(ddrin[1]),
(.D(ddrin[2]),
(.D(ddrin[3]),
(.D(ddrin[4]),
(.D(ddrin[5]),
(.D(ddrin[6]),
(.D(ddrin[7]),
.ECLK(dqsbuf),
.ECLK(dqsbuf),
.ECLK(dqsbuf),
.ECLK(dqsbuf),
.ECLK(dqsbuf),
.ECLK(dqsbuf),
.ECLK(dqsbuf),
10-22
.SCLK(clk),
.SCLK(clk),
.SCLK(clk),
.SCLK(clk),
.SCLK(clk),
.SCLK(clk),
.SCLK(clk),
LatticeECP/EC and LatticeXP
.CE(vcc_net),
.CE(vcc_net),
.CE(vcc_net),
.CE(vcc_net),
.CE(vcc_net),
.CE(vcc_net),
.CE(vcc_net),
DDR Usage Guide
.DDRCLK-
.DDRCLK-
.DDRCLK-
.DDRCLK-
.DDRCLK-
.DDRCLK-
.DDRCLK-