LFXP3C-3TN144I Lattice, LFXP3C-3TN144I Datasheet - Page 325
LFXP3C-3TN144I
Manufacturer Part Number
LFXP3C-3TN144I
Description
FPGA - Field Programmable Gate Array 3.1K LUTs 100 I/O 1.8/2.5/3.3V IND
Manufacturer
Lattice
Specifications of LFXP3C-3TN144I
Number Of Programmable I/os
100
Data Ram Size
55296
Supply Voltage (max)
3.465 V
Maximum Operating Temperature
+ 100 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Supply Voltage (min)
1.71 V
Package / Case
TQFP-144
Package
144TQFP
Family Name
LatticeXP
Device Logic Units
3000
Maximum Internal Frequency
320 MHz
Typical Operating Supply Voltage
1.8|2.5|3.3 V
Maximum Number Of User I/os
100
Ram Bits
55296
Re-programmability Support
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFXP3C-3TN144I
Manufacturer:
INTEL
Quantity:
1 143
Company:
Part Number:
LFXP3C-3TN144I
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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Lattice ispTRACY Usage Guide
Figure 14-9. ispLA Project Setup Window - Trigger Setup options
The options available in the Trigger setup window are based on selected ispTRACY core options. In the Trace
Mode box, One Shot mode will always be available, but Sample After Trigger availability is dependent on selecting
Sample_After_Trigger Mode Logic => ON. The position slider can be used to select the trigger point anywhere
within the data memory depth. There are three preconfigured trigger positions in the drop-down menu box. They
are Pre-Trigger (5% before and 95% after trigger), Center (50% before and 50% after trigger) and Post Trigger
(95% before and 5% after trigger). In the Compare Mode box the options are also dependant on core configuration.
EV0 and EV1 are always available. The comparisons available and number of samples will be determined by the
Size Comparison Logic and Event Counter Size. The equal to comparison is always available. Additions compari-
sons include >, <. !=, <=, >=. The Trigger Condition box configures which event or combination of events will cause
the ispLA program to trigger and upload captured data from the device. In a simple case, this would be set to Wait
for EV0. More complex cases could possible be wait for EV0 and EV1, or after EV1 wait until EV0. The final two
boxed on this screen control the signal polarity of Trigger In (if available) and Trigger Out.
14-7
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