LFXP3C-3TN144I Lattice, LFXP3C-3TN144I Datasheet - Page 171
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LFXP3C-3TN144I
Manufacturer Part Number
LFXP3C-3TN144I
Description
FPGA - Field Programmable Gate Array 3.1K LUTs 100 I/O 1.8/2.5/3.3V IND
Manufacturer
Lattice
Specifications of LFXP3C-3TN144I
Number Of Programmable I/os
100
Data Ram Size
55296
Supply Voltage (max)
3.465 V
Maximum Operating Temperature
+ 100 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Supply Voltage (min)
1.71 V
Package / Case
TQFP-144
Package
144TQFP
Family Name
LatticeXP
Device Logic Units
3000
Maximum Internal Frequency
320 MHz
Typical Operating Supply Voltage
1.8|2.5|3.3 V
Maximum Number Of User I/os
100
Ram Bits
55296
Re-programmability Support
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFXP3C-3TN144I
Manufacturer:
INTEL
Quantity:
1 143
Company:
Part Number:
LFXP3C-3TN144I
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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Memory Usage Guide
Lattice Semiconductor
LatticeECP/EC and LatticeXP Devices
Figure 9-6. Generating Pseudo Dual Port RAM (RAM_DP) Module Customization – Configuration Tab
Users can specify the Address Depth and Data width for the Read Port and the Write Port in the text boxes pro-
vided. In this example we are generating a Pseudo Dual Port RAM of size 512 x 16. Users can also create RAMs of
different port widths in the case of Pseudo Dual Port and True Dual Port RAMs.
The check box Enable Output Registers inserts the output registers in the Read Data Port, as the output registers
are optional for the EBR-based RAMs.
The Reset Mode can be selected to be Asynchronous Reset or Synchronous Reset. GSR or Global Set Reset can
be checked to be Enabled or Disabled.
The Input Data and the Address Control is always registered, as the hardware only supports synchronous opera-
tion for the EBR based RAMs
Users can also pre-initialize their memory with the contents they specify in the Memory file. It is optional to provide
this file in the RAMs. However, in the case of ROM, it is required to provide the Memory file. These files can be of
Binary, Hex or Addresses Hex format. The details of these formats are discussed in the Initialization File section of
this technical note.
At this point, users can click the Generate button to generate the module that they have customized. A netlist in the
desired format is then generated and placed in the specified location. Users can incorporate this netlist in their
designs.
Users can check the Import LPC to ispLEVER project check box to automatically import the file in the Project Nav-
igator.
Once the Module is generated, users can either instantiate the *.lpc or the Verilog-HDL/ VHDL file in the top level
module of their design.
The various memory modules, both EBR and Distributed, are discussed in detail later in this document.
9-6
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