LFXP3C-3TN144I Lattice, LFXP3C-3TN144I Datasheet - Page 255

• Manufacturer Part Number: LFXP3C-3TN144I
• Description: FPGA - Field Programmable Gate Array 3.1K LUTs 100 I/O 1.8/2.5/3.3V IND
• Manufacturer: Lattice

Specifications of LFXP3C-3TN144I

• Number Of Programmable I/os: 100
• Data Ram Size: 55296
• Supply Voltage (max): 3.465 V
• Maximum Operating Temperature: + 100 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.71 V
• Package / Case: TQFP-144
• Package: 144TQFP
• Family Name: LatticeXP
• Device Logic Units: 3000
• Maximum Internal Frequency: 320 MHz
• Typical Operating Supply Voltage: 1.8|2.5|3.3 V
• Maximum Number Of User I/os: 100
• Ram Bits: 55296
• Re-programmability Support: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

LatticeECP/EC and LatticeXP
Lattice Semiconductor
DDR Usage Guide
Appendix F. DDR400 Interface using the LatticeEC Evaluation Board
The DDR400 interface was implemented using the LatticeEC20 device on the LatticeEC Advanced Evaluation
Board. Figures 10-21, 10-22 and 10-23 show the READ, WRITE and WRITE to READ transition operations running
at 200MHz. For more information on the evaluation board, refer to LatticeEC Advanced Evaluation Board User’s
Guide available on the Lattice web site at www.latticesemi.com.
Figure 10-21. READ Function Running at 200MHz
Note: An extra READ command is implemented in the LatticeEC20 device to protect the data during postamble.
This extra READ is not required for other LatticeEC devices. Refer to the DQS Postamble section of this document
for more information.
10-36