LFXP3C-3TN144I Lattice, LFXP3C-3TN144I Datasheet - Page 322
LFXP3C-3TN144I
Manufacturer Part Number
LFXP3C-3TN144I
Description
FPGA - Field Programmable Gate Array 3.1K LUTs 100 I/O 1.8/2.5/3.3V IND
Manufacturer
Lattice
Specifications of LFXP3C-3TN144I
Number Of Programmable I/os
100
Data Ram Size
55296
Supply Voltage (max)
3.465 V
Maximum Operating Temperature
+ 100 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Supply Voltage (min)
1.71 V
Package / Case
TQFP-144
Package
144TQFP
Family Name
LatticeXP
Device Logic Units
3000
Maximum Internal Frequency
320 MHz
Typical Operating Supply Voltage
1.8|2.5|3.3 V
Maximum Number Of User I/os
100
Ram Bits
55296
Re-programmability Support
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
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Manufacturer
Quantity
Price
Company:
Part Number:
LFXP3C-3TN144I
Manufacturer:
INTEL
Quantity:
1 143
Company:
Part Number:
LFXP3C-3TN144I
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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Lattice Semiconductor
Lattice ispTRACY Usage Guide
ispTRACY Core Linker
Once the ispTRACY core is created, it must be linked into the target design. This is accomplished through the Core
Linker program. The Core Linker program allows the user access to internal and external signals of the target
design. The internal signals can be named signals or component ports. This window also displays the available isp-
TRACY ports. To connect ispTRACY signals, the desired signal(s) are selected in the left-hand signal window. Sig-
nals chosen from this window are reflected in the Selected signals window. Signals must be highlighted in this
window, the ispTRACY port window and then click on the connect button to connect the signals in the RTL code.
Multiple instances (for example, a data bus) can be connected at once by highlighting the first signal, holding down
the SHIFT key and clicking on the last desired signal. Figure 14-4 shows the ispTRACY Core Linker window.
Figure 14-4. ispTRACY Core Linker Program Window
When you click the Save button (or File -> Save menu selection), the Core Linker will create modified versions of
your source file, with the ispTRACY core linked into these modified files. Only design files that are directly con-
nected to the core will be modified. A dialogue box will indicate which files have been changed and will need to be
replaced in the design project for ispTRACY to function. The design files names will be the original files names with
the module name for the ispTRACY core (from the IPexpress ispTRACY core generation) appended. Figure 14-5
shows the changed files dialogue box.
14-4
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