LFXP3C-3TN144I Lattice, LFXP3C-3TN144I Datasheet - Page 374

• Manufacturer Part Number: LFXP3C-3TN144I
• Description: FPGA - Field Programmable Gate Array 3.1K LUTs 100 I/O 1.8/2.5/3.3V IND
• Manufacturer: Lattice

Specifications of LFXP3C-3TN144I

• Number Of Programmable I/os: 100
• Data Ram Size: 55296
• Supply Voltage (max): 3.465 V
• Maximum Operating Temperature: + 100 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.71 V
• Package / Case: TQFP-144
• Package: 144TQFP
• Family Name: LatticeXP
• Device Logic Units: 3000
• Maximum Internal Frequency: 320 MHz
• Typical Operating Supply Voltage: 1.8|2.5|3.3 V
• Maximum Number Of User I/os: 100
• Ram Bits: 55296
• Re-programmability Support: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
From the Set-up Report below, which was run for MAX conditions. The report shown here is for ddr_ad.
Find delays similarly for ddr_ras_n, ddr_cas_n, ddr_we_n, ddr_ba, ddr_cs_n and ddr_cke signals. Then take the
max of those delays as t
============================================================================================
Preference: CLOCK_TO_OUT PORT “ddr_ad_*” 5.500000 ns CLKNET “ddr_clk_c” ;
Passed:
ddr_clk_c -)
IN_DEL
ROUTE
MCLK_DEL
ROUTE
OUTREG_DEL
NCLK_DEL
ROUTE
Report:
Logical Details:
Constraint Details:
Physical Path Details:
Source:
Destination:
Data Path Delay:
Clock Path Delay:
Name
Name
Name
•
t
6.392ns delay clk to ddr_ad_6 less
3.271ns feedback compensation
1.713ns delay ddr_ad_6 to ddr_ad_6 (totaling 4.834ns) meets
5.500ns offset clk to ddr_ad_6 by 0.666ns
Clock path clk to ddr_ad_6:
Data path ddr_ad_6 to ddr_ad_6:
Feedback path:
CCTRL
The following path meets requirements by 0.666ns
Fanout
Fanout
Fanout
4.834ns is the minimum offset for this preference.
(max) =
12 items scored, 0 timing errors detected.
---
---
449
---
---
136
1
--------
--------
--------
(6.392-3.271)
Unknown
Cell type
Port
CCTRL
Delay (ns)
1.431
0.816
0.385
3.760
6.392
Delay (ns)
1.713
1.713
Delay (ns)
0.385
2.886
3.271
1.713ns
6.392ns
(max).
LLHPPLL.CLKIN to
LLHPPLL.CLKIN to
LLHPPLL.MCLK to
(28.4% logic, 71.6% route), 2 logic levels.
(100.0% logic, 0.0% route), 1 logic levels.
LLHPPLL.NCLK to
(11.8% logic, 88.2% route), 1 logic levels.
Q
+ 1.713 = 4.834 ns
Pin type
Pad
AB4.INCK to
(100.0% logic, 0.0% route), 1 logic levels.
(28.4% logic, 71.6% route), 2 logic levels.
AB4.PAD to
AE14.SC to
Site
Site
Site
18-14
U1_ddrct_np_o4_1_008/U1_cmdexe/ddr_adZ0Z_6
Cell name
ddr_ad_6
LLHPPLL.CLKIN clk_c
LLHPPLL.MCLK U2_ddr_pll_orca/ddr_pll_0_0
LLHPPLL.NCLK U2_ddr_pll_orca/ddr_pll_0_0
LLHPPLL.FB pll_nclk
AB4.INCK clk
AE14.PAD ddr_ad_6 (from ddr_clk_c)
AE14.SC ddr_clk_c
for the DDR SDRAM Controller IP Core
(clock net +/-)
Resource
Resource
Resource
Board Timing Guidelines
(from