LFXP3C-3TN144I Lattice, LFXP3C-3TN144I Datasheet - Page 273

• Manufacturer Part Number: LFXP3C-3TN144I
• Description: FPGA - Field Programmable Gate Array 3.1K LUTs 100 I/O 1.8/2.5/3.3V IND
• Manufacturer: Lattice

Specifications of LFXP3C-3TN144I

• Number Of Programmable I/os: 100
• Data Ram Size: 55296
• Supply Voltage (max): 3.465 V
• Maximum Operating Temperature: + 100 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.71 V
• Package / Case: TQFP-144
• Package: 144TQFP
• Family Name: LatticeXP
• Device Logic Units: 3000
• Maximum Internal Frequency: 320 MHz
• Typical Operating Supply Voltage: 1.8|2.5|3.3 V
• Maximum Number Of User I/os: 100
• Ram Bits: 55296
• Re-programmability Support: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Use of DCS with PLL
The four PLL CLKOP sources reach CLK0 and CLK1 of the quadrant clock. When using the DCS, the PLL needs a
free-running feedback path to keep the PLL in lock. The user should use CLKOP as this feedback path, and
CLKOS as the input into the DCS. CLKOP does not reach CLK2 or CLK3 to prevent the user from using the PLL
improperly with DCS. See Figure 11-14.
Figure 11-14. Implementation of Dynamic Clock Select for a PLL Clock (Must Use Both CLKOP and CLKOS)
Other Design Considerations
Jitter Considerations
The Clock Output jitter specifications assume that the reference clock is free of jitter. Even if the clock source is
clean, there are a number of sources that place noise in the PLL clock input. While intrinsic jitter is not avoidable,
there are ways to minimize the input jitter and output jitter.
Signal inputs that share the same I/O bank with PLL clock inputs are preferably less noisy inputs and slower switch-
ing signals. Try to avoid placing any high speed and noisy signals in the same I/O bank with clock signals if possi-
ble. Use differential signaling if possible.
When external feedback is used, the PCB path must be well designed to avoid reflection as well as noise coupling
from adjacent signal sources. A shorter PCB feedback path length does not necessarily reduce feedback input jit-
ter.
Simulation Limitations
• Simulation does not compensate for external delays and dividers in the feedback loop.
• The LOCK signal is not simulated according to the t
• The jitter specifications are not included.
shortly after the simulation begins, but will remain active throughout the simulation.
DCSOUT
SEL
CLK1
- Switch high at CLK1 rising edge.
- If SEL is low, output stays low high
on CLK1 falling edge.
DCS MODE = HIGH_HIGH
CLKI
CLKFB
PLL
CLKOS
CLKOP
(set 0°)
11-17
LOCK
CLK2 ISB
CLK2 ISB
DCSOUT
SEL
sysCLOCK PLL Design and Usage Guide
CLK0
specification. The LOCK signal will appear active
CLK0 ISB
- Switch high at CLK0 rising edge.
- If SEL is high, output stays high on
CLK0 falling edge.
DCS MODE = LOW_HIGH
D
C
S
LatticeECP/EC and LatticeXP
CLK2
CLK0