LFXP3C-3TN144I Lattice, LFXP3C-3TN144I Datasheet - Page 3

• Manufacturer Part Number: LFXP3C-3TN144I
• Description: FPGA - Field Programmable Gate Array 3.1K LUTs 100 I/O 1.8/2.5/3.3V IND
• Manufacturer: Lattice

Specifications of LFXP3C-3TN144I

• Number Of Programmable I/os: 100
• Data Ram Size: 55296
• Supply Voltage (max): 3.465 V
• Maximum Operating Temperature: + 100 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.71 V
• Package / Case: TQFP-144
• Package: 144TQFP
• Family Name: LatticeXP
• Device Logic Units: 3000
• Maximum Internal Frequency: 320 MHz
• Typical Operating Supply Voltage: 1.8|2.5|3.3 V
• Maximum Number Of User I/os: 100
• Ram Bits: 55296
• Re-programmability Support: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Pinout Information
Ordering Information
Supplemental Information
LatticeXP Family Data Sheet Revision History
Section II. LatticeXP Family Technical Notes
LatticeECP/EC and LatticeXP sysIO Usage Guide
sysIO Single-Ended DC Electrical Characteristics............................................................................................. 3-8
sysIO Differential Electrical Characteristics ....................................................................................................... 3-9
Differential HSTL and SSTL............................................................................................................................. 3-10
Typical Building Block Function Performance.................................................................................................. 3-14
Derating Logic Timing ...................................................................................................................................... 3-15
LatticeXP External Switching Characteristics .................................................................................................. 3-16
LatticeXP Internal Timing Parameters ............................................................................................................. 3-18
Timing Diagrams .............................................................................................................................................. 3-20
EBR Memory Timing Diagrams........................................................................................................................ 3-21
LatticeXP Family Timing Adders ...................................................................................................................... 3-23
sysCLOCK PLL Timing .................................................................................................................................... 3-25
LatticeXP sysCONFIG Port Timing Specifications........................................................................................... 3-26
Flash Download Time ...................................................................................................................................... 3-27
JTAG Port Timing Specifications ..................................................................................................................... 3-27
Switching Test Conditions................................................................................................................................ 3-28
Signal Descriptions ............................................................................................................................................ 4-1
PICs and DDR Data (DQ) Pins Associated with the DDR Strobe (DQS) Pin .................................................... 4-3
Pin Information Summary................................................................................................................................... 4-4
Power Supply and NC Connections................................................................................................................... 4-6
LFXP3 Logic Signal Connections: 100 TQFP .................................................................................................... 4-7
LFXP3 & LFXP6 Logic Signal Connections: 144 TQFP................................................................................... 4-10
LFXP3 & LFXP6 Logic Signal Connections: 208 PQFP .................................................................................. 4-14
LFXP6 & LFXP10 Logic Signal Connections: 256 fpBGA................................................................................ 4-19
LFXP15 & LFXP20 Logic Signal Connections: 256 fpBGA.............................................................................. 4-26
LFXP10, LFXP15 & LFXP20 Logic Signal Connections: 388 fpBGA............................................................... 4-34
LFXP15 & LFXP20 Logic Signal Connections: 484 fpBGA.............................................................................. 4-43
Thermal Management ...................................................................................................................................... 4-56
Part Number Description.................................................................................................................................... 5-1
Ordering Information (Contact Factory for Specific Device Availability)............................................................. 5-1
For Further Information ...................................................................................................................................... 6-1
Revision History ................................................................................................................................................. 7-1
Introduction ........................................................................................................................................................ 8-1
sysIO Buffer Overview ....................................................................................................................................... 8-1
Supported sysIO Standards ............................................................................................................................... 8-1
sysIO Banking Scheme...................................................................................................................................... 8-2
LVDS......................................................................................................................................................... 3-9
LVDS25E ................................................................................................................................................ 3-10
BLVDS .................................................................................................................................................... 3-10
LVPECL .................................................................................................................................................. 3-12
RSDS ...................................................................................................................................................... 3-12
Pin-to-Pin Performance (LVCMOS25 12 mA Drive) ............................................................................... 3-14
Register to Register Performance........................................................................................................... 3-14
PFU Timing Diagrams............................................................................................................................. 3-20
For Further Information ........................................................................................................................... 4-56
Conventional Packaging ........................................................................................................................... 5-2
Lead-free Packaging ................................................................................................................................. 5-8
V
CCIO
(1.2V/1.5V/1.8V/2.5V/3.3V) ............................................................................................................ 8-3
2
LatticeXP Family Handbook
Table of Contents