DP83865DVH National Semiconductor, DP83865DVH Datasheet - Page 37

• Manufacturer Part Number: DP83865DVH
• Description: 10/100/1000BASE-T TRANSCEIVER, SMD
• Manufacturer: National Semiconductor

Specifications of DP83865DVH

• Data Rate: 1000Mbps
• No. Of Ports: 1
• Ethernet Type: IEEE 802.3u, IEEE 802.3z
• Supply Current: 430µA
• Supply Voltage Range: 2.375V To 2.625V, 3.135V To 3.465V
• Operating Temperature Range: 0°C To +70°C
• Interface Type: GMII, MII, RGMII
• Rohs Compliant: Yes
• Leaded Process Compatible: No
• Peak Reflow Compatible (260 C): No
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

2.0 Register Block
15:0
2:0
Bit
Bit
Bit
15
14
13
12
11
10
15
14
13
12
11
9
8
7
6
5
4
3
mas_sla_err_int_clr
nxt_pg_rcvd_int_clr
rem_flt_cng_int_clr
jabber_cng_int_clr
prl_det_flt_int_clr
mdix_cng_int_clr
dplx_cng_int_clr
spd_cng_int_clr
an_cmpl_int_clr
tx_bist_pak_len
lnk_cng_int_clr
pol_cng_int_clr
no_hcd_int_clr
no_lnk_int_clr
BIST Counter
bist_cnt_type
bist_cnt_clr
tx_bist_ifg
tx_bist_en
Bit Name
Reserved
Bit Name
Bit Name
Table 24. BIST Configuration Register 1 (BIST_CFG1) address 0x19 (25’d)
Table 22. Interrupt Clear Register (INT_CLEAR) address 0x17 (23’d)
Table 23. BIST Counter Register (BIST_CNT) address 0x18 (24’d)
(Continued)
0, RW, SC
0, RW, SC
0, RW, SC
0, RW, SC
0, RW, SC
0, RW, SC
0, RW, SC
0, RW, SC
0, RW, SC
0, RW, SC
0, RW, SC
0, RW, SC
0, RW, SC
0, RW, SC
0, RW, SC
Default
Default
Default
0, RW
0, RW
0, RW
0, RO
0, RO
Setting this bit clears the spd_cng_int interrupt.
Setting this bit clears the lnk_cng_int interrupt.
Setting this bit clears the dplx_cng_int interrupt.
Setting this bit clears the mdix_cng_int interrupt.
Setting this bit clears the pol_cng_int interrupt.
Setting this bit clears the prl_det_flt_int interrupt.
Setting this bit clears the mas_sla_err_int interrupt.
Setting this bit clears the no_hcd_int interrupt.
Setting this bit clears the no_lnk_int interrupt.
Setting this bit clears the jabber_cng_int interrupt.
Setting this bit clears the nxt_pg_rcvd_int interrupt.
Setting this bit clears the an_cmpl_int interrupt.
Setting this bit clears the rem_flt_cng_int interrupt.
Write as 0, ignore on read.
BIST Counter: This register counts receive packets or receive
errors according to bit 15 in register BIST_CFG1. It shows either
the upper or lower 16 bit of a 32 bit value which can be selected
through bit 14 in register BIST_CFG2.
Set BIST Counter Type:
1 = BIST_CNT counts receive CRC errors
0 = BIST_CNT counts receive packets
BIST Counter Clear: Setting this bit clears the BIST_CNT regis-
ter to 0.
Transmit BIST Packet Length:
1 = 1514 bytes
0 = 60 bytes
Transmit BIST Interframe Gap: This bit sets the IFG for transmit
BIST packets.
1 = 9.6 us
0 = 0.096us
Transmit BIST Enable: This bit starts the transmit BIST. The
number of selected packets or a continous data stream is sent out
when set. This bit self-clears after the packets have been sent.
1 = Transmit BIST enabled
0 = Transmit BIST disabled
37
Description
Description
Description
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