EVAL-ADUC842QSZ Analog Devices Inc, EVAL-ADUC842QSZ Datasheet



Manufacturer Part Number
Analog MCU Evaluation Board
Analog Devices Inc
QuickStart™ Kitr

Specifications of EVAL-ADUC842QSZ

Silicon Manufacturer
Analog Devices
Core Architecture
Silicon Core Number
Tool / Board Applications
General Purpose MCU, MPU, DSP, DSC
Mcu Supported Families
Evaluation Board, Power Supply, Cable, Software and Documentation
Development Tool Type
Hardware - Eval/Demo Board
Rohs Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Pin compatable ugrade of ADuC812/ADuC831/ADuC832
Analog I/O
8052 based core
High performance single-cycle core
On-chip peripherals
Development tools
Optical networking—laser power control
Base station systems
Precision instrumentation, smart sensors
Transient capture systems
DAS and communications systems
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
ADuC841/ADuC842 only.
ADuC842/ADuC843 only, ADuC841 driven directly by external crystal.
Increased performance
Increased memory
In-circuit reprogrammable
Smaller package
8-channel, 420 kSPS high accuracy, 12-bit ADC
On-chip, 15 ppm/°C voltage reference
DMA controller, high speed ADC-to-RAM capture
Two 12-bit voltage output DACs
Dual output PWM ∑-∆ DACs
On-chip temperature monitor function
8051 compatible instruction set (20 MHz max)
32 kHz external crystal, on-chip programmable PLL
12 interrupt sources, 2 priority levels
Dual data pointers, extended 11-bit stack pointer
Time interval counter (TIC)
Watchdog timer (WDT)
Power supply monitor (PSM)
Normal: 4.5 mA @ 3 V (core CLK = 2.098 MHz)
Power-down: 10 µA @ 3 V
Low cost, comprehensive development system
incorporating nonintrusive single-pin emulation,
IDE based assembly and C source debugging
Single-cycle 20 MIPS 8052 core
High speed 420 kSPS 12-bit ADC
Up to 62 kBytes on-chip Flash/EE program memory
4 kBytes on-chip Flash/EE data memory
Flash/EE, 100 year retention, 100 kCycle endurance
2304 bytes on-chip data RAM
8 mm × 8 mm chip scale package
52-lead PQFP—pin compatable upgrade
C®, and SPI® Serial I/O
Embedded High Speed 62-kB Flash MCU
The ADuC841/ADuC842/ADuC843 are complete smart
transducer front ends, that integrates a high performance self-
calibrating multichannel ADC, a dual DAC, and an optimized
single-cycle 20 MHz 8-bit MCU (8051 instruction set
compatible) on a single chip.
The ADuC841 and ADuC842 are identical with the exception of
the clock oscillator circuit; the ADuC841 is clocked directly
from an external crystal up to 20 MHz whereas the ADuC842
uses a 32 kHz crystal with an on-chip PLL generating a
programmable core clock up to 16.78 MHz.
The ADuC843 is identical to the ADuC842 except that the
ADuC843 has no analog DAC outputs.
The microcontroller is an optimized 8052 core offering up to
20 MIPS peak performance. Three different memory options
are available offering up to 62 kBytes of nonvolatile Flash/EE
program memory. Four kBytes of nonvolatile Flash/EE data
memory, 256 bytes RAM, and 2 kBytes of extended RAM are
also integrated on-chip.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.326.8703
12-Bit ADCs and DACs with
(continued on page 15)
© 2003 Analog Devices, Inc. All rights reserved.
Figure 1.

Related parts for EVAL-ADUC842QSZ

EVAL-ADUC842QSZ Summary of contents

Page 1

... Watchdog timer (WDT) Power supply monitor (PSM) Power Normal: 4 (core CLK = 2.098 MHz) 2 Power-down: 10 µ Development tools Low cost, comprehensive development system incorporating nonintrusive single-pin emulation, IDE based assembly and C source debugging APPLICATIONS Optical networking—laser power control Base station systems ...

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... Watchdog Timer......................................................................... 53 Time Interval Counter (TIC).................................................... 54 8052 Compatible On-Chip Peripherals................................... 57 Timer/Counter 0 and 1 Operating Modes.............................. 62 Timer/Counter Operating Modes............................................ 64 UART Serial Interface................................................................ 65 SBUF ............................................................................................ 65 Interrupt System ......................................................................... 70 Hardware Design Considerations ............................................ 72 Other Hardware Considerations.............................................. 76 Development Tools .................................................................... 77 QuickStart Development System ............................................. Timing Specifications .................................................................. 78 Outline Dimensions ....................................................................... 86 Ordering Guides......................................................................... 87 Rev Page ...

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SPECIFICATIONS Table all specifications unless otherwise noted A MIN MAX Parameter ADC CHANNEL SPECIFICATIONS ...

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ADuC841/ADuC842/ADuC843 Parameter DAC AC CHARACTERISTICS Voltage Output Settling Time Digital-to-Analog Glitch Energy 12, 13 DAC CHANNEL SPECIFICATIONS Internal Buffer Disabled ADuC841/ADuC842 Only 10 DC ACCURACY Resolution Relative Accuracy 11 Differential Nonlinearity Offset Error Gain Error 4 Gain Error Mismatch ANALOG ...

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Parameter 4 LOGIC INPUTS INPUT VOLTAGES All Inputs Except SCLOCK, SDATA, RESET, and XTAL1 VINL, Input Low Voltage VINH, Input High Voltage SDATA VINL, Input Low Voltage VINH, Input High Voltage 4 SCLOCK and RESET Only (Schmitt-Triggered Inputs ...

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ADuC841/ADuC842/ADuC843 Parameter 19, 20 POWER REQUIREMENTS Power Supply Voltages AV /DV – AGND DD DD Power Supply Currents Normal Mode 4 DV Current DD AV Current DD DV Current DD AV Current DD DV Current Power Supply ...

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Temperature Range –40°C to +85°C. 2 ADC linearity is guaranteed during normal MicroConverter core operation ADC LSB size = i.e., for internal LSB = 610 µV, and for external ...

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ADuC841/ADuC842/ADuC843 ABSOLUTE MAXIMUM RATINGS Table 25°C, unless otherwise noted A Parameter AGND to DGND DV to DGND AGND DD DD Digital Input Voltage to DGND Digital Output Voltage to DGND ...

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ADuC841/ADuC842/ADuC843 Mnemonic Type Function P3.0–P3.7 I/O Port bidirectional port with internal pull-up resistors. Port 3 pins that have 1s written to them are pulled high by the internal pull-up resistors, and in that state can be used ...

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TERMINOLOGY ADC SPECIFICATIONS Integral Nonlinearity The maximum deviation of any code from a straight line passing through the endpoints of the ADC transfer function. The endpoints of the transfer function are zero scale, a point ½ LSB below the first ...

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ADuC841/ADuC842/ADuC843 TYPICAL PERFORMANCE CHARACTERISTICS The typical performance plots presented in this section illustrate typical performance of the ADuC841/ADuC842/ ADuC843 under various operating conditions. Figure 5 and Figure 6 show typical ADC integral nonlinearity (INL) errors from ADC Code 0 to ...

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AV 0 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 0 511 1023 1535 2047 2559 ADC CODES Figure 7. Typical INL Error 1.0 AV 0.8 f ...

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ADuC841/ADuC842/ADuC843 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 0.5 1.0 1.5 2.0 EXTERNAL REFERENCE (V) Figure 13. Typical Worst-Case DNL Error vs. V 0.7 0.5 0.3 0.1 –0.1 –0.3 –0.5 –0.7 0.5 1.0 1.5 2.0 EXTERNAL REFERENCE (V) Figure 14. ...

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EXTERNAL REFERENCE (V) Figure 19. Typical Dynamic Performance vs 0.5 1.0 1.5 2.0 EXTERNAL REFERENCE (V) Figure 20. Typical Dynamic Performance ...

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ADuC841/ADuC842/ADuC843 FUNCTIONAL DESCRIPTION 8052 INSTRUCTION SET Table 4 documents the number of clock cycles required for each instruction. Most instructions are executed in one or two clock cycles, resulting MIPS peak performance when operating at PLLCON = ...

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Mnemonic Description XRL A,dir Exclusive-OR indirect memory to A XRL dir,#data Exclusive-OR immediate data to direct CLR A Clear A CPL A Complement A SWAP A Swap nibbles Rotate A left RLC A Rotate A left ...

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ADuC841/ADuC842/ADuC843 Mnemonic Description Branching JMP @A+DPTR Jump indirect relative to DPTR RET Return from subroutine RETI Return from interrupt ACALL addr11 Absolute jump to subroutine AJMP addr11 Absolute jump unconditional SJMP rel Short jump (relative address) JC rel Jump on ...

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MEMORY ORGANIZATION The ADuC841/ADuC842/ADuC843 each contain four different memory blocks: • kBytes of on-chip Flash/EE program memory • 4 kBytes of on-chip Flash/EE data memory • 256 bytes of general-purpose RAM • 2 kBytes of internal XRAM ...

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ADuC841/ADuC842/ADuC843 07FFH CFG841 CFG841 CFG842 CFG842 100H FFH 256 BYTES OF ON-CHIP DATA RAM ON-CHIP XRAM (DATA + STACK) 00H 00H Figure 24. Extended Stack Pointer Operation External Data Memory (External XRAM) ...

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ACCUMULATOR SFR (ACC) ACC is the accumulator register and is used for math opera- tions including addition, subtraction, integer multiplication and division, and Boolean bit manipulations. The mnemonics for accumulator-specific instructions refer to the accumulator SFR (B) ...

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ADuC841/ADuC842/ADuC843 SPECIAL FUNCTION REGISTER BANKS All registers except the program counter and the four general- purpose register banks reside in the special function register (SFR) area. The SFR registers include control, configuration, and data registers, which provide an interface between ...

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ADC CIRCUIT INFORMATION General Overview The ADC conversion block incorporates a fast, 8-channel, 12-bit, single-supply ADC. This block provides the user with multichannel mux, track-and-hold, on-chip reference, calibra- tion features, and ADC. All components in this block are easily configured ...

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ADuC841/ADuC842/ADuC843 ADCCON1—(ADC Control SFR 1) The ADCCON1 register controls conversion and acquisition times, hardware conversion modes, and power-down modes as detailed below. SFR Address EFH SFR Power-On Default 40H Bit Addressable No Table 7. ADCCON1 SFR Bit Designations Bit No. ...

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ADCCON2—(ADC Control SFR 2) The ADCCON2 register controls ADC channel selection and conversion modes as detailed below. SFR Address D8H SFR Power-On Default 00H Bit Addressable Yes Table 8. ADCCON2 SFR Bit Designations Bit No. Name Description 7 ADCI ADC ...

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ADuC841/ADuC842/ADuC843 ADCCON3—(ADC Control SFR 3) The ADCCON3 register controls the operation of various calibration modes and also indicates the ADC busy status. SFR Address F5H SFR Power-On Default 00H Bit Addressable No Table 9. ADCCON3 SFR Bit Designations Bit No. ...

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The ADC incorporates a successive approximation architecture (SAR) involving a charge-sampled input stage. Figure 30 shows the equivalent circuit of the analog input section. Each ADC conversion is divided into two distinct phases, as defined by the position of the ...

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ADuC841/ADuC842/ADuC843 Table 11. Some Single-Supply Op Amps Op Amp Model Characteristics OP281/OP481 Micropower OP191/OP291/OP491 I/O Good OP196/OP296/OP496 I Micropower, Low Cost DD OP183/OP283 High Gain-Bandwidth Product OP162/OP262/OP462 High GBP, Micro Package AD820/AD822/AD824 FET Input, ...

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If using the temperature sensor as the ADC input, the ADC should be configured to use an ADCCLK of MCLK/32 and four acquisition clocks. Increasing the conversion time on the temperature monitor channel improves the accuracy of the reading. To ...

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ADuC841/ADuC842/ADuC843 The DMA logic operates from the ADC clock and uses pipelin- ing to perform the ADC conversions and to access the external memory at the same time. The time it takes to perform one ADC conversion is called a ...

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Initiating the Calibration in Code When calibrating the ADC using ADCCON1, the ADC must be set up into the configuration in which it will be used. The ADCCON3 register can then be used to set up the device and to ...

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ADuC841/ADuC842/ADuC843 A 4 kByte Flash/EE data memory space is also provided on- chip. This may be used as a general-purpose nonvolatile scratchpad area. User access to this area is via a group of six SFRs. This space can be programmed ...

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User Download Mode (ULOAD) Figure 39 shows that it is possible to use the 62 kBytes of Flash/EE program memory available to the user as a single block of memory. In this mode, all of the Flash/EE memory is read-only ...

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ADuC841/ADuC842/ADuC843 USING FLASH/EE DATA MEMORY The 4 kBytes of Flash/EE data memory are configured as 1024 pages, each of 4 bytes. As with the other ADuC841/ADuC842/ ADuC843 peripherals, the interface to this memory space is via a group of registers ...

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Example: Programming the Flash/EE Data Memory A user wants to program F3H into the second byte on Page 03H of the Flash/EE data memory space while preserving the other 3 bytes already in this page. A typical program of the ...

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ADuC841/ADuC842/ADuC843 ADuC842/ADuC843 Configuration SFR (CFG842) The CFG842 SFR contains the necessary bits to configure the internal XRAM, external clock select, PWM output selection, DAC buffer, and the extended SP for both the ADuC842 and the ADuC843. By default, it configures ...

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CFG841 ADuC841 Config SFR SFR Address AFH 1 Power-On Default 10H Bit Addressable No Table 14. CFG841 SFR Bit Designations Bit No. Name Description 7 EXSP Extended SP Enable. When set the user, the stack rolls over ...

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ADuC841/ADuC842/ADuC843 USER INTERFACE TO ON-CHIP PERIPHERALS This section gives a brief overview of the various peripherals also available on-chip. A summary of the SFRs used to control and configure these peripherals is also given. DAC The ADuC841/ADuC842 incorporate two 12-bit ...

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Using the DAC The on-chip DAC architecture consists of a resistor string DAC followed by an output buffer amplifier, the functional equivalent of which is illustrated in Figure 42. Details of the actual DAC architecture can be found in U.S. ...

Page 40

ADuC841/ADuC842/ADuC843 The endpoint nonlinearities illustrated in Figure 43 become worse as a function of output loading. Most of the part’s specifications assume a 10 kΩ resistive load to ground at the DAC output. As the output is forced to source ...

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ON-CHIP PLL The ADuC842 and ADuC843 are intended for use with a 32.768 kHz watch crystal. A PLL locks onto a multiple (512) of this to provide a stable 16.78 MHz clock for the system. The ADuC841 operates directly from ...

Page 42

ADuC841/ADuC842/ADuC843 PULSE-WIDTH MODULATOR (PWM) The PWM on the ADuC841/ADuC842/ADuC843 is a highly flexible PWM offering programmable resolution and an input clock, and can be configured for any one of six different modes of operation. Two of these modes allow the ...

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PWM Modes of Operation Mode 0: PWM Disabled The PWM is disabled allowing P2.6 and P2 used as normal. Mode 1: Single Variable Resolution PWM In Mode 1, both the pulse length and the cycle time (period) are ...

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ADuC841/ADuC842/ADuC843 Mode 4: Dual NRZ 16-Bit ∑-∆ DAC Mode 4 provides a high speed PWM output similar to that of a -∆ DAC. Typically, this mode is used with the PWM clock ∑ equal to 16.777216 MHz. In this mode, ...

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SERIAL PERIPHERAL INTERFACE (SPI) The ADuC841/ADuC842/ADuC843 integrate a complete hard- ware serial peripheral interface on-chip. SPI is an industry- standard synchronous serial interface that allows 8 bits of data to be synchronously transmitted and received simultaneously, i.e., full duplex. Note ...

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ADuC841/ADuC842/ADuC843 SPICON SPI Control Register SFR Address F8H Power-On Default 04H Bit Addressable Yes Table 18. SPICON SFR Bit Designations Bit No. Name Description 7 ISPI SPI Interrupt Bit. Set by the MicroConverter at the end of each SPI transfer. ...

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Using the SPI Interface Depending on the configuration of the bits in the SPICON SFR shown in Table 18, the ADuC841/ADuC842/ADuC843 SPI interface transmits or receives data in a number of possible modes. Figure 54 shows all possible SPI configurations ...

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ADuC841/ADuC842/ADuC843 COMPATIBLE INTERFACE The ADuC841/ADuC842/ADuC843 support a fully licensed serial interface. The I C interface is implemented as a full hardware slave and software master. SDATA is the data I/O pin, and SCLOCK ...

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Bit No. Name Description 2 2 I2CRS I C Reset Bit (Slave Mode Only). Set by the user to reset the I Cleared by the user code for normal I2CTX I C Direction Transfer Bit (Slave Mode ...

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ADuC841/ADuC842/ADuC843 • slave can respond to repeated start conditions without a stop bit in between. This allows a master to change direction of transfer without giving up the bus. Note that the repeated start is detected ...

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DUAL DATA POINTER The ADuC841/ADuC842/ADuC843 incorporate two data pointers. The second data pointer is a shadow data pointer and is selected via the data pointer control SFR (DPCON). DPCON also includes some useful features such as automatic hardware post-increment and ...

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ADuC841/ADuC842/ADuC843 POWER SUPPLY MONITOR As its name suggests, the power supply monitor, once enabled, monitors the DV supply on the ADuC841/ADuC842/ DD ADuC843. It indicates when any of the supply pins drops below one of two user selectable voltage trip ...

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WATCHDOG TIMER The purpose of the watchdog timer is to generate a device reset or interrupt within a reasonable amount of time if the ADuC841/ ADuC842/ADuC843 enter an erroneous state, possibly due to a programming error or electrical noise. The ...

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ADuC841/ADuC842/ADuC843 TIME INTERVAL COUNTER (TIC) A TIC is provided on-chip for counting longer intervals than the standard 8051 compatible timers are capable of. The TIC is capable of timeout intervals ranging from 1/128 second to 255 hours. Furthermore, this counter ...

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TIMECON TIC Control Register SFR Address A1H Power-On Default 00H Bit Addressable No Table 24. TIMECON SFR Bit Designations Bit No. Name Description 7 ---- Reserved. 6 TFH Twenty-Four Hour Select Bit. Set by the user to enable the hour ...

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ADuC841/ADuC842/ADuC843 INTVAL User Time Interval Select Register Function User code writes the required time interval to this register. When the 8-bit interval counter is equal to the time interval value loaded in the INTVAL SFR, the TII bit (TIMECON.2) is ...

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COMPATIBLE ON-CHIP PERIPHERALS This section gives a brief overview of the various secondary peripheral circuits that are also available to the user on-chip. These remaining functions are mostly 8052 compatible (with a few additional features) and are controlled via ...

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ADuC841/ADuC842/ADuC843 In general-purpose I/O port mode, Port 2 pins that have 1s written to them are pulled high by the internal pull-ups (Figure 60) and, in that state, can be used as inputs. As inputs, Port 2 pins being pulled ...

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MOSI is shared with P3.3 and, as such, has the same configuration as the one shown in Figure 61 SPE = ENABLE) 2 HARDWARE (SLAVE ONLY) (OFF) SFR 50ns GLITCH BITS REJECTION ...

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ADuC841/ADuC842/ADuC843 Timers/Counters The ADuC841/ADuC842/ADuC843 have three 16-bit timer/ counters: Timer 0, Timer 1, and Timer 2. The timer/counter hardware is included on-chip to relieve the processor core of the overhead inherent in implementing timer/counter functionality in software. Each timer/counter consists ...

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Timer/Counter 0 and 1 TCON Control Register SFR Address 88H Power-On Default 00H Bit Addressable Yes Table 29. TCON SFR Bit Designations Bit No. Name Description 7 TF1 Timer 1 Overflow Flag. Set by hardware on a Timer/Counter 1 overflow. ...

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ADuC841/ADuC842/ADuC843 TIMER/COUNTER 0 AND 1 OPERATING MODES The following sections describe the operating modes for Timer/Counters 0 and 1. Unless otherwise noted, assume that these modes of operation are the same for both Timer 0 and Timer 1. Mode 0 ...

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T2CON Timer/Counter 2 Control Register SFR Address C8H Power-On Default 00H Bit Addressable Yes Table 30. T2CON SFR Bit Designations Bit No. Name Description 7 TF2 Timer 2 Overflow Flag. Set by hardware on a Timer 2 overflow. TF2 cannot ...

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ADuC841/ADuC842/ADuC843 TIMER/COUNTER OPERATING MODES The following sections describe the operating modes for Timer/Counter 2. The operating modes are selected by bits in the T2CON SFR, as shown in Table 31. Table 31. T2CON Operating Modes RCLK (or) TCLK CAP2 TR2 ...

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UART SERIAL INTERFACE The serial port is full-duplex, meaning it can transmit and receive simultaneously also receive-buffered, meaning it can begin receiving a second byte before a previously received byte has been read from the receive register. However, ...

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ADuC841/ADuC842/ADuC843 Mode 0: 8-Bit Shift Register Mode Mode 0 is selected by clearing both the SM0 and SM1 bits in the SFR SCON. Serial data enters and exits through RxD. TxD out- puts the shift clock. Eight data bits are ...

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Mode 3: 9-Bit UART with Variable Baud Rate Mode 3 is selected by setting both SM0 and SM1. In this mode, the 8051 UART serial port operates in 9-bit mode with a vari- able baud rate determined by either Timer ...

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ADuC841/ADuC842/ADuC843 Timer 3 Generated Baud Rates The high integer dividers in a UART block mean that high speed baud rates are not always possible using some particular crystals. For example, using a 12 MHz crystal, a baud rate of 115200 ...

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Table 34. Commonly Used Baud Rates Using Timer 3 with the 16.777216 MHz PLL Clock Ideal Baud CD 230400 0 115200 0 115200 1 115200 2 57600 0 57600 1 57600 2 57600 3 38400 0 38400 1 38400 2 ...

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ADuC841/ADuC842/ADuC843 INTERRUPT SYSTEM The ADuC841/ADuC842/ADuC843 provide a total of nine interrupt sources with two priority levels. The control and configuration of the interrupt system is carried out through three interrupt-related SFRs: IE Interrupt Enable Register IP Interrupt Priority Register Secondary ...

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IEIP2 Secondary Interrupt Enable Register SFR Address A9H Power-On Default A0H Bit Addressable No Table 37. IEIP2 SFR Bit Designations Bit No. Name Description 7 ---- Reserved. 6 PTI Priority for time interval interrupt. 5 PPSM Priority for power supply ...

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ADuC841/ADuC842/ADuC843 HARDWARE DESIGN CONSIDERATIONS This section outlines some of the key hardware design considerations that must be addressed when integrating the ADuC841/ADuC842/ADuC843 into any hardware system. Clock Oscillator The clock source for the parts can be generated by the internal ...

Page 73

If access to more than 64 kBytes of RAM is desired, a feature unique to the ADuC841/ADuC842/ADuC843 allows address- ing MBytes of external RAM simply by adding an additional latch as illustrated in Figure 79. ADuC841/ ADuC842/ ...

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ADuC841/ADuC842/ADuC843 Power Consumption The currents consumed by the various sections of the part are shown in Table 40. The core values given represent the current drawn while the rest (ADC, DAC, voltage ref) are DD pulled by ...

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V Part For DV below 4.5 V, the internal POR holds the part in reset rises above 4 internal timer times out for DD approximately 128 ms before the part is released from reset. ...

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ADuC841/ADuC842/ADuC843 ANALOG INPUT AV DD VREF OUTPUT DAC OUTPUT ADM202 C1+ V+ C1– C2+ C2– V– T2OUT R2IN Figure 85. Example System (PQFP Package), DACs Not Present on ADuC843 OTHER HARDWARE CONSIDERATIONS To facilitate in-circuit programming, plus in-circuit debug and ...

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... The QuickStart Development System is an entry-level, low cost development tool suite supporting the parts. The system consists of the following PC based (Windows® compatible) hardware and software development tools. Hardware Evaluation board and serial port programming cable. Software Serial download software. Miscellaneous CD-ROM documentation and prototype device ...

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ADuC841/ADuC842/ADuC843 TIMING SPECIFICATIONS Table 41 unless otherwise noted Parameter ADuC842/ADuC843 CLOCK INPUT (External Clock Driven XTAL1) t XTAL1 Period CK t XTAL1 Width Low CKL t ...

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Parameter EXTERNAL DATA MEMORY READ CYCLE t RD Pulse Width RLRH t Address Valid after ALE Low AVLL t Address Hold after ALE Low LLAX t RD Low to Valid Data In RLDV t Data and Address Hold after RD ...

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ADuC841/ADuC842/ADuC843 Parameter EXTERNAL DATA MEMORY WRITE CYCLE t WR Pulse Width WLWH t Address Valid after ALE Low AVLL t Address Hold after ALE Low LLAX t ALE Low Low LLWL t Address Valid to RD ...

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Parameter COMPATIBLE INTERFACE TIMING t SCLOCK Low Pulse Width L t SCLOCK High Pulse Width H t Start Condition Hold Time SHD t Data Setup Time DSU t Data Hold Time DHD t Setup Time for Repeated ...

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ADuC841/ADuC842/ADuC843 Parameter SPI MASTER MODE TIMING (CPHA = 1) t SCLOCK Low Pulse Width SL t SCLOCK High Pulse Width SH t Data Output Valid after SCLOCK Edge DAV t Data Input Setup Time before SCLOCK Edge DSU t Data ...

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Parameter SPI MASTER MODE TIMING (CPHA = 0) t SCLOCK Low Pulse Width SL t SCLOCK High Pulse Width SH t Data Output Valid after SCLOCK Edge DAV t Data Output Setup before SCLOCK Edge DOSU t Data Input Setup ...

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ADuC841/ADuC842/ADuC843 Parameter SPI SLAVE MODE TIMING (CPHA = SCLOCK Edge SS t SCLOCK Low Pulse Width SL t SCLOCK High Pulse Width SH t Data Output Valid after SCLOCK Edge DAV t Data Input Setup Time ...

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Parameter SPI SLAVE MODE TIMING (CPHA = SCLOCK Edge SS t SCLOCK Low Pulse Width SL t SCLOCK High Pulse Width SH t Data Output Valid after SCLOCK Edge DAV t Data Input Setup Time before ...

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ADuC841/ADuC842/ADuC843 OUTLINE DIMENSIONS 2.10 2.00 1.95 VIEW A ROTATED 90° CCW PIN 1 INDICATOR 1.00  12° MAX 0.85 0.80 SEATING PLANE 1.03 2.45 0.88 MAX 0. SEATING PLANE 7.80 REF VIEW A PIN 7° ...

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... EVAL-ADuC842QSP 5 1 The only difference between the ADuC842 and ADuC843 parts is the voltage output DACs on the ADuC842; thus the evaluation system for the ADuC842 is also suitable for the ADuC843. 2 The Quickstart Plus system can only be ordered directly from Accutron. It can be purchased from the website www.accutron.com. ...

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ADuC841/ADuC842/ADuC843 Notes Purchase of licensed components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I 2 Rights to use these components system, ...

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