EVAL-ADUC842QSZ Analog Devices Inc, EVAL-ADUC842QSZ Datasheet - Page 49

• Manufacturer Part Number: EVAL-ADUC842QSZ
• Description: Analog MCU Evaluation Board
• Manufacturer: Analog Devices Inc
• Series: QuickStart™ Kitr
• Type: MCUr

Specifications of EVAL-ADUC842QSZ

• Silicon Manufacturer: Analog Devices
• Core Architecture: 8052
• Silicon Core Number: ADuC842
• Tool / Board Applications: General Purpose MCU, MPU, DSP, DSC
• Mcu Supported Families: ADUC8xx
• Contents: Evaluation Board, Power Supply, Cable, Software and Documentation
• Development Tool Type: Hardware - Eval/Demo Board
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: ADuC824
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Bit No.
2
1
0
I2CADD
Function
SFR Address
Power-On Default
Bit Addressable
I2CADD1
Function
SFR Address
Power-On Default
Bit Addressable
I2CADD2
Function
SFR Address
Power-On Default
Bit Addressable
I2CADD3
Function
SFR Address
Power-On Default
Bit Addressable
I2CDAT
Function
SFR Address
Power-On Default
Bit Addressable
The main features of the MicroConverter I
•
•
Only two bus lines are required: a serial data line (SDATA)
and a serial clock line (SCLOCK).
An I
devices. Because each slave device has a unique 7-bit
2
C master can communicate with multiple slave
Name
I2CRS
I2CTX
I2CI
Description
I
Set by the user to reset the I
Cleared by the user code for normal I
I
Set by the MicroConverter if the interface is transmitting.
Cleared by the MicroConverter if the interface is receiving.
I
Set by the MicroConverter after a byte has been transmitted or received.
Cleared automatically when user code reads the I2CDAT SFR (see I2CDAT below).
2
2
2
C Reset Bit (Slave Mode Only).
C Direction Transfer Bit (Slave Mode Only).
C Interrupt Bit (Slave Mode Only).
I
Holds the first I
uC001 at www.analog.com/microconverter describes the format of the I
detail.
9BH
55H
No
I
Holds the second I
91H
7FH
No
I
Holds the third I
92H
7FH
No
I
Holds the fourth I
93H
7FH
No
I
Written by the user to transmit data over the I
received by the I
the I2CI bit in the I2CCON SFR. User software should access I2CDAT only once per interrupt cycle.
9AH
00H
No
2
2
2
2
2
C Address Register
C Address Register
C Address Register
C Address Register
C Data Register
2
C interface are
2
2
C peripheral address for the part. It may be overwritten by user code. Application Note
2
2
C interface. Accessing I2CDAT automatically clears any pending I
C interface.
C peripheral address for the part. It may be overwritten by user code.
2
2
C peripheral address for the part. It may be overwritten by user code.
C peripheral address for the part. It may be overwritten by user code.
2
C operation.
Rev. 0 | Page 49 of 88
•
address, single master/slave relationships can exist at all
times even in a multislave environment.
Ability to respond to four separate addresses when
operating in slave mode.
2
C interface or read by user code to read data just
ADuC841/ADuC842/ADuC843
2
C standard 7-bit address in
2
C interrupt and