EVAL-ADUC842QSZ Analog Devices Inc, EVAL-ADUC842QSZ Datasheet - Page 71

• Manufacturer Part Number: EVAL-ADUC842QSZ
• Description: Analog MCU Evaluation Board
• Manufacturer: Analog Devices Inc
• Series: QuickStart™ Kitr
• Type: MCUr

Specifications of EVAL-ADUC842QSZ

• Silicon Manufacturer: Analog Devices
• Core Architecture: 8052
• Silicon Core Number: ADuC842
• Tool / Board Applications: General Purpose MCU, MPU, DSP, DSC
• Mcu Supported Families: ADUC8xx
• Contents: Evaluation Board, Power Supply, Cable, Software and Documentation
• Development Tool Type: Hardware - Eval/Demo Board
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: ADuC824
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

IEIP2
SFR Address
Power-On Default
Bit Addressable
Table 37. IEIP2 SFR Bit Designations
Bit No.
7
6
5
4
3
2
1
0
Interrupt Priority
The interrupt enable registers are written by the user to enable
individual interrupt sources, while the interrupt priority regis-
ters allow the user to select one of two priority levels for each
interrupt. An interrupt of a high priority may interrupt the
service routine of a low priority interrupt, and if two interrupts
of different priority occur at the same time, the higher level
interrupt is serviced first. An interrupt cannot be interrupted by
another interrupt of the same priority level. If two interrupts of
the same priority level occur simultaneously, a polling sequence
is observed as shown in Table 38.
Table 38. Priority within an Interrupt Level
Source
PSMI
WDS
IE0
ADCI
TF0
IE1
TF1
ISPI/I2CI
RI + TI
TF2 + EXF2
TII
Name
----
PTI
PPSM
PSI
----
ETI
EPSMI
ESI
Priority
1 (Highest)
2
2
3
4
5
6
7
8
9
11(Lowest)
Description
Reserved.
Priority for time interval interrupt.
Priority for power supply monitor interrupt.
Priority for SPI/I
This bit must contain zero.
Set by the user to enable, or cleared to disable time interval counter interrupts.
Set by the user to enable, or cleared to disable power supply monitor interrupts.
Set by the user to enable, or cleared to disable SPI or I
Description
Power Supply Monitor Interrupt.
Watchdog Timer Interrupt.
External Interrupt 0.
ADC Interrupt.
Timer/Counter 0 Interrupt.
External Interrupt 1.
Timer/Counter 1 Interrupt.
SPI Interrupt/I
Serial Interrupt.
Timer/Counter 2 Interrupt.
Time Interval Counter Interrupt.
Secondary Interrupt Enable Register
A9H
A0H
No
2
C interrupt.
2
C Interrupt.
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Interrupt Vectors
When an interrupt occurs, the program counter is pushed onto
the stack, and the corresponding interrupt vector address is
loaded into the program counter. The interrupt vector addresses
are shown in Table 39.
Table 39. Interrupt Vector Addresses
Source
IE0
TF0
IE1
TF1
RI + TI
TF2 + EXF2
ADCI
ISPI/I2CI
PSMI
TII
WDS
2
C serial port interrupts.
ADuC841/ADuC842/ADuC843
Vector Address
0003H
000BH
0013H
001BH
0023H
002BH
0033H
003BH
0043H
0053H
005BH