AD9520-3BCPZ Analog Devices Inc, AD9520-3BCPZ Datasheet - Page 13

• Manufacturer Part Number: AD9520-3BCPZ
• Description: 12/24 Channel Clock Gen 2,0GH
• Manufacturer: Analog Devices Inc
• Type: Clock Generator, Fanout Distributionr

Specifications of AD9520-3BCPZ

• Design Resources: Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers (CN0121) Phase Coherent FSK Modulator (CN0186)
• Pll: Yes
• Input: CMOS, LVDS, LVPECL
• Output: CMOS, LVPECL
• Number Of Circuits: 1
• Ratio - Input:output: 2:12, 2:24
• Differential - Input:output: Yes/Yes
• Frequency - Max: 2.25GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LFCSP
• Frequency-max: 2.25GHz
• Function: Clock Generator
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Package Type: LFCSP EP
• Pin Count: 64
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

CLOCK OUTPUT ADDITIVE TIME JITTER (VCO DIVIDER USED)
Table 12.
Parameter
LVPECL OUTPUT ADDITIVE TIME JITTER
CMOS OUTPUT ADDITIVE TIME JITTER
SERIAL CONTROL PORT—SPI MODE
Table 13.
Parameter
CS (INPUT)
SCLK (INPUT) IN SPI MODE
SDIO (WHEN AN INPUT IN BIDIRECTIONAL MODE)
SDIO, SDO (OUTPUTS)
TIMING
CLK = 1.0 GHz; VCO DIV = 5; LVPECL = 100 MHz;
CLK = 500 MHz; VCO DIV = 5; LVPECL = 100 MHz;
CLK = 200 MHz; VCO DIV = 2; CMOS = 100 MHz;
CLK = 1600 MHz; VCO DIV = 2; CMOS = 100 MHz;
Input Logic 1 Voltage
Input Logic 0 Voltage
Input Logic 1 Current
Input Logic 0 Current
Input Capacitance
Input Logic 1 Voltage
Input Logic 0 Voltage
Input Logic 1 Current
Input Logic 0 Current
Input Capacitance
Input Logic 1 Voltage
Input Logic 0 Voltage
Input Logic 1 Current
Input Logic 0 Current
Input Capacitance
Output Logic 1 Voltage
Output Logic 0 Voltage
Clock Rate (SCLK, 1/t
Pulse Width High, t
Pulse Width Low, t
SDIO to SCLK Setup, t
SCLK to SDIO Hold, t
SCLK to Valid SDIO and SDO, t
CS to SCLK Setup and Hold, t
CS Minimum Pulse Width High, t
Divider = 2; Duty-Cycle Correction = Off
Bypass Channel Divider; Duty-Cycle Correction = On
Bypass Channel Divider; Duty-Cycle Correction = Off
Divider = 8; Duty-Cycle Correction = Off
LOW
HIGH
DH
SCLK
DS
)
S
, t
DV
C
PWH
Min
2.7
16
16
4
0
2
3
2.0
2.0
2.0
Min
Typ
−110
2
110
2
1
1
2
Rev. 0 | Page 13 of 84
Typ
230
215
326
362
Max
0.8
3
0.8
1
0.8
0.4
25
11
Max
Unit
V
V
μA
μA
pF
V
V
μA
μA
pF
V
V
μA
μA
pF
V
V
MHz
ns
ns
ns
ns
ns
ns
ns
Unit
fs rms
fs rms
fs rms
fs rms
Test Conditions/Comments
CS has an internal 30 kΩ pull-up resistor
The minus sign indicates that current is flowing out of
the AD9520, which is due to the internal pull-up resistor
SCLK has an internal 30 kΩ pull-down resistor in SPI
mode, but not in I
Test Conditions/Comments
Distribution section only; does not include PLL and
VCO; uses rising edge of clock signal
Calculated from SNR of ADC method (broadband
jitter)
Calculated from SNR of ADC method (broadband
jitter)
Distribution section only; does not include PLL and
VCO; uses rising edge of clock signal
Calculated from SNR of ADC method (broadband
jitter)
Calculated from SNR of ADC method (broadband
jitter)
2
C mode
AD9520-3