AD9520-3BCPZ Analog Devices Inc, AD9520-3BCPZ Datasheet - Page 76

• Manufacturer Part Number: AD9520-3BCPZ
• Description: 12/24 Channel Clock Gen 2,0GH
• Manufacturer: Analog Devices Inc
• Type: Clock Generator, Fanout Distributionr

Specifications of AD9520-3BCPZ

• Design Resources: Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers (CN0121) Phase Coherent FSK Modulator (CN0186)
• Pll: Yes
• Input: CMOS, LVDS, LVPECL
• Output: CMOS, LVPECL
• Number Of Circuits: 1
• Ratio - Input:output: 2:12, 2:24
• Differential - Input:output: Yes/Yes
• Frequency - Max: 2.25GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LFCSP
• Frequency-max: 2.25GHz
• Function: Clock Generator
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Package Type: LFCSP EP
• Pin Count: 64
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Reg.
Addr
(Hex) Bit(s) Name
190
190
191
191
191
191
191
AD9520-3
Reg.
Addr
(Hex) Bit(s) Name
0F6
0F7
0F8
0F9
0FA
0FB
0FC
0FC
0FC
0FC
0FC
0FC
0FC
0FC
0FD
0FD
0FD
0FD
Table 55. LVPECL Channel Dividers
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
[3]
[2]
[1]
[0]
[7:4]
[3:0]
[7]
[6]
[5]
[4]
[3:0]
OUT6 control
OUT7 control
OUT8 control
OUT9 control
OUT10 control This register controls OUT10, and the bit assignments for this register are identical to Register 0x0F0.
OUT11 control This register controls OUT11, and the bit assignments for this register are identical to Register 0x0F0.
CSDLD En OUT7 Output 7 enabled only if CSDLD is high.
CSDLD En OUT6 Output 6 enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7].
CSDLD En OUT5 Output 5 enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7].
CSDLD En OUT4 Output 4 enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7].
CSDLD En OUT3 Output 3 enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7].
CSDLD En OUT2 Output 2 enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7].
CSDLD En OUT1 Output 1 enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7].
CSDLD En OUT0 Output 0 enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7].
CSDLD En
OUT11
CSDLD En
OUT10
CSDLD En OUT9 Output 9 enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7].
CSDLD En OUT8 Output 8 enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7].
Divider 0 low cycles
Divider 0 high cycles
Divider 0 bypass
Divider 0 ignore SYNC
Divider 0 force high
Divider 0 start high
Divider 0 phase offset
Description
This register controls OUT6, and the bit assignments for this register are identical to Register 0x0F0.
This register controls OUT7, and the bit assignments for this register are identical to Register 0x0F0.
This register controls OUT8, and the bit assignments for this register are identical to Register 0x0F0.
This register controls OUT9, and the bit assignments for this register are identical to Register 0x0F0.
[7]
0
1
1
Output 11 enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7].
Output 10 enabled only if CSDLD is high. Setting is identical to Register 0x0FC[7].
Description
Number of clock cycles (minus 1) of the divider input during which divider output stays low.
A value of 0x7 means the divider is low for eight input clock cycles (default: 0x7).
Number of clock cycles (minus 1) of the divider input during which divider output stays high.
A value of 0x7 means the divider is high for eight input clock cycles (default: 0x7).
Bypasses and powers down the divider; routes input to divider output.
[7] = 0; use divider (default).
[7] = 1; bypass divider.
No SYNC.
[6] = 0; obey chip-level SYNC signal (default).
[6] = 1; ignore chip-level SYNC signal.
Forces divider output to high. This requires that no SYNC also be set.
[5] = 0; divider output forced to low (default).
[5] = 1; divider output forced to high.
Selects clock output to start high or start low.
[4] = 0; start low (default).
[4] = 1; start high.
Phase offset (default: 0x0).
CSDLD Signal Output 7 Enable Status
0
0
1
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Not affected by CSDLD signal (default).
Asynchronous power-down.
Asynchronously enable Output 7 if not powered down by other settings.
To use this feature, the user must use current source digital lock detect,
and set the enable LD pin comparator bit (0x01D[3]).