AD9520-3BCPZ Analog Devices Inc, AD9520-3BCPZ Datasheet - Page 48

• Manufacturer Part Number: AD9520-3BCPZ
• Description: 12/24 Channel Clock Gen 2,0GH
• Manufacturer: Analog Devices Inc
• Type: Clock Generator, Fanout Distributionr

Specifications of AD9520-3BCPZ

• Design Resources: Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers (CN0121) Phase Coherent FSK Modulator (CN0186)
• Pll: Yes
• Input: CMOS, LVDS, LVPECL
• Output: CMOS, LVPECL
• Number Of Circuits: 1
• Ratio - Input:output: 2:12, 2:24
• Differential - Input:output: Yes/Yes
• Frequency - Max: 2.25GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LFCSP
• Frequency-max: 2.25GHz
• Function: Clock Generator
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Package Type: LFCSP EP
• Pin Count: 64
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9520-3
The pipeline delay from the SYNC rising edge to the beginning
of the synchronized output clocking is between 14 cycles and
15 cycles of clock at the channel divider input, plus either one
cycle of the VCO divider input (see
the channel divider input (see
the VCO divider is used. Cycles are counted from the rising
edge of the signal. In addition, there is an additional 1.2 ns (typical)
delay from the SYNC signal to the internal synchronization logic,
as well as the propagation delay of the output driver. The driver
propagation delay is approximately 100 ps for the LVPECL
driver and approximately 1.5 ns for the CMOS driver.
Another common way to execute the SYNC function is by
setting and resetting the soft SYNC bit at 0x230[0]. Both setting
and resetting of the soft SYNC bit require an update all registers
(0x232[0] = 1) operation to take effect.
A SYNC operation brings all outputs that have not been excluded
(by the ignore SYNC bit) to a preset condition before allowing
SYNC PIN
INPUT TO CHANNEL DIVIDER
SYNC PIN
INPUT TO CHANNEL DIVIDER
INPUT TO VCO DIVIDER
CHANNEL DIVIDER
CHANNEL DIVIDER
OUTPUT CLOCKING
OUTPUT CLOCKING
CHANNEL DIVIDER
CHANNEL DIVIDER
INPUT TO CLK
OUTPUT OF
OUTPUT OF
Figure 52
Figure 51. SYNC Timing Pipeline Delay When VCO Divider Is Used—CLK or VCO Is Input
Figure 52. SYNC Timing Pipeline Delay When VCO Divider Is Not Used—CLK Input Only
Figure 51
), depending on whether
), or one cycle of
1
1
14 TO 15 CYCLES AT CHANNEL DIVIDER INPUT + 1 CYCLE AT VCO DIVIDER INPUT
14 TO 15 CYCLES AT CHANNEL DIVIDER INPUT + 1 CYCLE AT CLK INPUT
2
2
3
3
CHANNEL DIVIDER OUTPUT STATIC
CHANNEL DIVIDER OUTPUT STATIC
Rev. 0 | Page 48 of 84
4
4
5
5
6
6
the outputs to begin clocking in synchronicity. The preset condition
takes into account the settings in each of the channel’s start high
bit and its phase offset. These settings govern both the static state
of each output when the SYNC operation is happening and the
state and relative phase of the outputs when they begin clocking
again upon completion of the SYNC operation. Between outputs
and after synchronization, this allows for the setting of phase offsets.
The AD9520 differential LVPECL outputs are four groups of
three, sharing a channel divider per triplet. In the case of CMOS,
each LVPECL differential pair can be configured as two single-
ended CMOS outputs. The synchronization conditions apply to
all of the drivers that belong to that channel divider.
Each channel (a divider and its outputs) can be excluded from
any SYNC operation by setting the no SYNC bit of the channel.
Channels that are set to ignore SYNC (excluded channels) do
not set their outputs static during a SYNC operation, and their
outputs are not synchronized with those of the included channels.
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
1
1
OUTPUT CLOCKING
OUTPUT CLOCKING
CHANNEL DIVIDER
CHANNEL DIVIDER