AD9520-3BCPZ Analog Devices Inc, AD9520-3BCPZ Datasheet - Page 16

12/24 Channel Clock Gen 2,0GH

AD9520-3BCPZ

Manufacturer Part Number
AD9520-3BCPZ
Description
12/24 Channel Clock Gen 2,0GH
Manufacturer
Analog Devices Inc
Type
Clock Generator, Fanout Distributionr
Datasheet

Specifications of AD9520-3BCPZ

Design Resources
Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers (CN0121) Phase Coherent FSK Modulator (CN0186)
Pll
Yes
Input
CMOS, LVDS, LVPECL
Output
CMOS, LVPECL
Number Of Circuits
1
Ratio - Input:output
2:12, 2:24
Differential - Input:output
Yes/Yes
Frequency - Max
2.25GHz
Divider/multiplier
Yes/No
Voltage - Supply
3.135 V ~ 3.465 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
64-LFCSP
Frequency-max
2.25GHz
Function
Clock Generator
Operating Temperature (max)
85C
Operating Temperature (min)
-40C
Package Type
LFCSP EP
Pin Count
64
Mounting
Surface Mount
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
AD9520-3
POWER DISSIPATION
Table 18.
Parameter
POWER DISSIPATION, CHIP
POWER DELTAS, INDIVIDUAL FUNCTIONS
Power-On Default
PLL Locked; One LVPECL Output Enabled
PLL Locked; One CMOS Output Enabled
Distribution Only Mode; VCO Divider On;
Distribution Only Mode; VCO Divider Off;
Maximum Power, Full Operation
PD Power-Down
PD Power-Down, Maximum Sleep
VCP Supply
VCO Divider On/Off
REFIN (Differential) Off
REF1, REF2 (Single-Ended) On/Off
VCO On/Off
PLL Dividers and Phase Detector On/Off
LVPECL Channel
LVPECL Driver
CMOS Channel
CMOS Driver On/Off
Channel Divider Enabled
Zero Delay Block On/Off
One LVPECL Output Enabled
One LVPECL Output Enabled
Min
4
Typ
1.32
0.55
0.52
0.39
0.36
1.5
60
24
32
25
15
67
51
121
51
145
11
40
30
Max
1.5
0.64
0.62
0.46
0.42
1.7
80
33
4.8
40
30
20
104
63
144
73
180
24
57
34
Rev. 0 | Page 16 of 84
Unit
W
W
W
W
W
W
mW
mW
mW
mW
mW
mW
mW
mW
mW
mW
mW
mW
mW
mW
Test Conditions/Comments
Does not include power dissipated in external resistors; all
LVPECL outputs terminated with 50 Ω to V
outputs have 10 pF capacitive loading; VS_DRV = 3.3 V
No clock; no programming; default register values
f
one LVPECL output and output divider enabled; zero delay off;
I
f
one CMOS output and output divider enabled; zero delay off;
I
f
one LVPECL output and output divider enabled; zero delay off
f
one LVPECL output and output divider enabled; zero delay off
PLL on; internal VCO = 160 MHz; VCO divider = 2; all channel
dividers on; 12 LVPECL outputs @ 125 MHz; zero delay on
PD pin pulled low; does not include power dissipated
in termination resistors
PD pin pulled low; PLL power-down 0x010[1:0] = 01b; SYNC
power-down 0x230[2] = 1b; power-down distribution reference
0x230[1] = 1b
PLL operating; typical closed-loop configuration
Power delta when a function is enabled/disabled
VCO divider not used
Delta between reference input off and differential reference
input mode
Delta between reference inputs off and one singled-ended
reference enabled; double this number if both REF1 and REF2
are powered up
Internal VCO disabled; CLK input selected
No LVPECL output on to one LVPECL output on; channel divider
set to 1
Second LVPECL output turned on, same channel
No CMOS output on to one CMOS output on; channel divider
set to 1; f
Additional CMOS outputs within the same channel turned on
Delta between divider bypassed (divide-by-1) and divide-by-2 to
divide-by-32
PLL off to PLL on, normal operation; no reference enabled
CP
CP
REF
REF
CLK
CLK
= 4.8 mA
= 4.8 mA
= 25 MHz; f
= 25 MHz; f
= 2.4 GHz; f
= 2 GHz; f
OUT
= 62.5 MHz and 10 pF of capacitive loading
OUT
OUT
OUT
OUT
= 200 MHz; VCO divider bypassed;
= 250 MHz; VCO = 2 GHz; VCO divider = 2;
= 62.5 MHz; VCO = 2 GHz; VCO divider = 2;
= 200 MHz; VCO divider = 2;
CC
− 2 V; all CMOS

Related parts for AD9520-3BCPZ