AD9520-3BCPZ Analog Devices Inc, AD9520-3BCPZ Datasheet - Page 74

• Manufacturer Part Number: AD9520-3BCPZ
• Description: 12/24 Channel Clock Gen 2,0GH
• Manufacturer: Analog Devices Inc
• Type: Clock Generator, Fanout Distributionr

Specifications of AD9520-3BCPZ

• Design Resources: Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers (CN0121) Phase Coherent FSK Modulator (CN0186)
• Pll: Yes
• Input: CMOS, LVDS, LVPECL
• Output: CMOS, LVPECL
• Number Of Circuits: 1
• Ratio - Input:output: 2:12, 2:24
• Differential - Input:output: Yes/Yes
• Frequency - Max: 2.25GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LFCSP
• Frequency-max: 2.25GHz
• Function: Clock Generator
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Package Type: LFCSP EP
• Pin Count: 64
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Reg.
Addr
(Hex) Bit(s) Name
01D
01D
01D
01D
01D
01D
01D
01E
01E
01E
01F
01F
01F
01F
AD9520-3
[7]
[6]
[5]
[4]
[3]
[1]
[0]
[4:3] External zero
[2]
[1]
[6]
[5]
[4]
[3]
Enable
Status_EEPROM
at STATUS pin
Enable
XTAL OSC
Enable clock
doubler
Disable PLL
status register
Enable LD pin
comparator
Enable external
holdover
Enable
holdover
delay
feedback
channel
divider select
Enable external
zero delay
Enable zero
delay
VCO calibration
finished
(read-only)
Holdover active
(read-only)
REF2 selected
(read-only)
VCO frequency
> threshold
(read-only)
Description
Enables the Status_EEPROM signal at the STATUS pin.
[7] = 0; the STATUS pin is controlled by 0x017[7:2] selection.
[7] = 1; select Status_EEPROM signal at STATUS pin. This bit overrides 0x017[7:2] (default).
Enables the maintaining amplifier needed by a crystal oscillator at the PLL reference input.
[6] = 0; crystal oscillator maintaining amplifier disabled (default).
[6] = 1; crystal oscillator maintaining amplifier enabled.
Enable PLL reference input clock doubler.
[5] = 0; doubler disabled (default).
[5] = 1; doubler enabled.
Disables the PLL status register readback.
[4] = 0; PLL status register enabled (default).
[4] = 1; PLL status register disabled. If this bit is set, Register 01F is not automatically updated.
Enables the LD pin voltage comparator. This is used with the LD pin current source lock detect mode.
When the AD9520 is in internal (automatic) holdover mode, this enables the use of the voltage on the
LD pin to determine if the PLL was previously in a locked state (see Figure 46). Otherwise, this can be used
with the REFMON and STATUS pins to monitor the voltage on this pin.
[3] = 0; disable LD pin comparator and ignore the LD pin voltage; internal/automatic holdover
controller treats this pin as true (high, default).
[3] = 1; enable LD pin comparator (use LD pin voltage to determine if the PLL was previously locked).
Enables the external hold control through the SYNC pin. (This disables the internal holdover mode.)
[1] = 0; automatic holdover mode, holdover controlled by automatic holdover circuit (default).
[1] = 1; external holdover mode, holdover controlled by SYNC pin.
Enables the internally controlled holdover function.
[0] = 0; holdover disabled (default).
[0] = 1; holdover enabled.
[4]
0
0
1
1
Selects which zero delay mode to use.
[2] = 0; enables internal zero delay mode if 0x01E[1] = 1 (default).
[2] = 1; enables external zero delay mode if 0x01E[1] = 1.
Enables zero delay function.
[1] = 0; disables zero delay function (default).
[1] = 1; enables zero delay function.
Readback register: status of the VCO calibration.
[6] = 0; VCO calibration not finished.
[6] = 1; VCO calibration finished.
Readback register. Indicates if the part is in the holdover state (see Figure 46). This is not the same as
holdover enabled.
[5] = 0; not in holdover.
[5] = 1; holdover state active.
Readback register. Indicates which PLL reference is selected as the input to the PLL.
[4] = 0; REF1 selected (or differential reference if in differential mode).
[4] = 1; REF2 selected.
Readback register. Indicates if the VCO frequency is greater than the threshold (see Table 17, REF1, REF2, and
VCO frequency status monitor parameter).
[3] = 0; VCO frequency is less than the threshold.
[3] = 1; VCO frequency is greater than the threshold.
[3]
0
1
0
1
Select Which Channel Divider to Use in the External Zero-Delay Path
Select Channel Divider 0 (default).
Select Channel Divider 1.
Select Channel Divider 2.
Select Channel Divider 3
Rev. 0 | Page 74 of 84