AD9520-3BCPZ Analog Devices Inc, AD9520-3BCPZ Datasheet - Page 14

• Manufacturer Part Number: AD9520-3BCPZ
• Description: 12/24 Channel Clock Gen 2,0GH
• Manufacturer: Analog Devices Inc
• Type: Clock Generator, Fanout Distributionr

Specifications of AD9520-3BCPZ

• Design Resources: Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers (CN0121) Phase Coherent FSK Modulator (CN0186)
• Pll: Yes
• Input: CMOS, LVDS, LVPECL
• Output: CMOS, LVPECL
• Number Of Circuits: 1
• Ratio - Input:output: 2:12, 2:24
• Differential - Input:output: Yes/Yes
• Frequency - Max: 2.25GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LFCSP
• Frequency-max: 2.25GHz
• Function: Clock Generator
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Package Type: LFCSP EP
• Pin Count: 64
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9520-3
SERIAL CONTROL PORT—I²C MODE
Table 14.
Parameter
SDA, SCL (WHEN INPUTS)
SDA (WHEN OUTPUTTING DATA)
TIMING
1
According to the original I
falling edge.
Input Logic 1 Voltage
Input Logic 0 Voltage
Input Current with an Input Voltage Between
Hysteresis of Schmitt Trigger Inputs
Pulse Width of Spikes That Must Be Suppressed by
Output Logic 0 Voltage at 3 mA Sink Current
Output Fall Time from VIH
Clock Rate (SCL, f
Bus Free Time Between a Stop and Start Condition, t
Setup Time for a Repeated Start Condition, t
Hold Time (Repeated) Start Condition (After This Period,
Setup Time for Stop Condition, t
Low Period of the SCL Clock, t
High Period of the SCL Clock, t
SCL, SDA Rise Time, t
SCL, SDA Fall Time, t
Data Setup Time, t
Data Hold Time, t
Capacitive Load for Each Bus Line, C
0.1 VS and 0.9 VS
the Input Filter, t
Capacitance from 10 pF to 400 pF
the First Clock Pulse Is Generated, t
I2C
HLD; DAT
SET; DAT
SPIKE
)
FALL
2
RISE
C specification, an I
MIN
to VIL
LOW
HIGH
SET; STP
MAX
b
2
HLD; STR
C master must also provide a minimum hold time of 300 ns for the SDA signal to bridge the undefined region of the SCL
with a Bus
)
SET; STR
IDLE
Rev. 0 | Page 14 of 84
Min
0.7 × VS
−10
0.015 × VS
20 + 0.1 C
capacitance of
one bus line in pF)
1.3
0.6
0.6
0.6
1.3
0.6
20 + 0.1 C
20 + 0.1 C
120
140
b
b
b
(C
b
=
Typ
Max
0.3 × VS
+10
50
0.4
250
400
300
300
880
400
Unit
V
V
μA
V
ns
V
ns
kHz
μs
μs
μs
μs
μs
μs
ns
ns
ns
ns
pF
Test Conditions/Comments
Note that all I
referred to VIH
VIL
This is a minor deviation from
the original I²C specification of
100 ns minimum
This is a minor deviation from
the original I²C specification of
0 ns minimum
MAX
levels (0.7 × VS)
2
C timing values
MIN
1
(0.3 × VS) and