AD9520-3BCPZ Analog Devices Inc, AD9520-3BCPZ Datasheet - Page 38

• Manufacturer Part Number: AD9520-3BCPZ
• Description: 12/24 Channel Clock Gen 2,0GH
• Manufacturer: Analog Devices Inc
• Type: Clock Generator, Fanout Distributionr

Specifications of AD9520-3BCPZ

• Design Resources: Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers (CN0121) Phase Coherent FSK Modulator (CN0186)
• Pll: Yes
• Input: CMOS, LVDS, LVPECL
• Output: CMOS, LVPECL
• Number Of Circuits: 1
• Ratio - Input:output: 2:12, 2:24
• Differential - Input:output: Yes/Yes
• Frequency - Max: 2.25GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LFCSP
• Frequency-max: 2.25GHz
• Function: Clock Generator
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Package Type: LFCSP EP
• Pin Count: 64
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9520-3
Digital Lock Detect (DLD)
By selecting the proper output through the mux on each pin, the
DLD function is available at the LD, STATUS, and REFMON pins.
The digital lock detect circuit indicates a lock when the time
difference of the rising edges at the PFD inputs is less than a
specified value (the lock threshold). The loss of a lock is indicated
when the time difference exceeds a specified value (the unlock
threshold). Note that the unlock threshold is wider than the
lock threshold, which allows some phase error in excess of the
lock window to occur without chattering on the lock indicator.
The lock detect window timing depends on the value of the
CPRSET resistor, as well as three settings: the digital lock detect
window bit (0x018[4]), the antibacklash pulse width bit
(0x017[1:0], see Table 2), and the lock detect counter
(0x018[6:5]). The lock and unlock detection values in Table 2
are for the nominal value of CPRSET = 5.11 kΩ. Doubling the
CPRSET value to 10 kΩ doubles the values in Table 2.
A lock is not indicated until there is a programmable number of
consecutive PFD cycles with a time difference less than the lock
detect threshold. The lock detect circuit continues to indicate a
lock until a time difference greater than the unlock threshold
occurs on a single subsequent cycle. For the lock detect to work
properly, the period of the PFD frequency must be greater than
the unlock threshold. The number of consecutive PFD cycles
required for lock is programmable (0x018[6:5]).
Note that it is possible in certain low (<500 Hz) loop bandwidth,
high phase margin cases that the DLD can chatter during acqui-
sition, which can cause the AD9520 to automatically enter and exit
holdover. To avoid this problem, it is recommended that the
user make provisions for a capacitor to ground on the LD pin so
that current source digital lock detect (CSDLD) mode can be used.
Analog Lock Detect (ALD)
The AD9520 provides an ALD function that can be selected for
use at the LD pin. There are two operating modes for ALD:
• N-channel open-drain lock detect. This signal requires a pull-
• P-channel open-drain lock detect. This signal requires a pull-
The analog lock detect function requires an R-C filter to provide a
logic level indicating lock/unlock. The ADIsimCLK tool can be
used to help the user select the right passive component values
for ALD to ensure its correct operation.
up resistor to the positive supply, VS. The output is normally
high with short, low-going pulses. Lock is indicated by the
minimum duty cycle of the low-going pulses.
down resistor to GND. The output is normally low with short,
high-going pulses. Lock is indicated by the minimum duty
cycle of the high-going pulses.
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Current Source Digital Lock Detect (CSDLD)
During the PLL locking sequence, it is normal for the DLD
signal to toggle a number of times before remaining steady
when the PLL is completely locked and stable. There may be
applications where it is desirable to have DLD asserted only
after the PLL is solidly locked. This is possible by using the
current source digital lock detect function. This function is
enabled by placing a capacitor to ground on the LD pin, and by
selecting DLD as the output for the LD pin
(0x01A[5:0] = 0x00).
Enabling the LD pin comparator (0x01D[3] = 1) allows the user:
• To use CSDLD in conjunction with automatic switchover
• To view the CSDLD status on the STATUS and REFMON pins.
The current source lock detect provides a current of 110 μA when
DLD is true and shorts to ground when DLD is false. If a capacitor
is connected to the LD pin, it charges at a rate determined by the
current source during the DLD true time but is discharged nearly
instantly when DLD is false. By monitoring the voltage at the
LD pin (top of the capacitor), LD = high happens only after the
DLD is true for a sufficiently long time. Any momentary DLD
false resets the charging. By selecting a properly sized capacitor,
it is possible to delay a lock detect indication until the PLL is
stably locked and the lock detect does not chatter.
The voltage on the capacitor can be sensed by an external
comparator connected to the LD pin. However, there is an
internal LD pin comparator that can be read at the REFMON
pin control (0x01B[4:0]) or the STATUS pin control (0x017[7:2])
as an active high signal. It is also available as an active low signal
(REFMON, 0x01B[4:0] and STATUS, 0x017[7:2]). The internal LD
pin comparator trip point and hysteresis are given in Table 17.
Using the CSDLD also allows the user to asynchronously enable
individual clock outputs only when CSDLD is high. To enable
this feature, set the appropriate bits in the enable output on the
CSDLD registers (0x0FC and 0x0FD).
and holdover.
Figure 43. Example of Analog Lock Detect Filter Using
ALD
AD9520
N-Channel Open-Drain Driver
LD
R1
VS = 3.3V
R2
C
V
OUT