AD9520-3BCPZ Analog Devices Inc, AD9520-3BCPZ Datasheet - Page 55

• Manufacturer Part Number: AD9520-3BCPZ
• Description: 12/24 Channel Clock Gen 2,0GH
• Manufacturer: Analog Devices Inc
• Type: Clock Generator, Fanout Distributionr

Specifications of AD9520-3BCPZ

• Design Resources: Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers (CN0121) Phase Coherent FSK Modulator (CN0186)
• Pll: Yes
• Input: CMOS, LVDS, LVPECL
• Output: CMOS, LVPECL
• Number Of Circuits: 1
• Ratio - Input:output: 2:12, 2:24
• Differential - Input:output: Yes/Yes
• Frequency - Max: 2.25GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LFCSP
• Frequency-max: 2.25GHz
• Function: Clock Generator
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Package Type: LFCSP EP
• Pin Count: 64
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The default mode of the AD9520 serial control port is the
bidirectional mode. In bidirectional mode, both the sent data
and the readback data appear on the SDIO pin. It is also possible to
set the AD9520 to unidirectional mode (0x000[7] = 1 and
0x000[0] = 1). In unidirectional mode, the readback data
appears on the SDO pin.
A readback request reads the data that is in the serial control
port buffer area, or the data in the active registers (see Figure 62).
Readback of the buffer or active registers is controlled by 0x004[0].
The AD9520 uses Register Address 0x000 to Register
Address 0xB03.
SPI INSTRUCTION WORD (16 BITS)
The MSB of the instruction word is R/
whether the instruction is a read or a write. The next two bits
(W1:W0) indicate the length of the transfer in bytes. The final
13 bits are the address (A12:A0) at which to begin the read or
write operation.
For a write, the instruction word is followed by the number of
bytes of data indicated by Bits W1:W0, see Table 43.
Table 43. Byte Transfer Count
W1
0
0
1
1
A12:A0: These 13 bits select the address within the register map
that is written to or read from during the data transfer portion
of the communications cycle. Only Bits[A9:A0] are needed to
cover the range of the 0x232 registers used by the AD9520.
Bits[A12:A10] must always be 0b. For multibyte transfers, this
address is the starting byte address. In MSB first mode, subsequent
bytes increment the address.
Figure 62. Relationship Between Serial Control Port Buffer Registers and
SCLK/SCL
SDIO/SDA
SDO
CS
W0
0
1
0
1
WRITE REGISTER 0x232 = 0x001
TO UPDATE REGISTERS
SERIAL
CONTROL
PORT
Active Registers of the AD9520
Bytes to Transfer
1
2
3
Streaming mode
REGISTERS
UPDATE
W
, which indicates
Rev. 0 | Page 55 of 84
SPI MSB/LSB FIRST TRANSFERS
The AD9520 instruction word and byte data can be MSB first
or LSB first. Any data written to 0x000 must be mirrored; the
upper four bits ([7:4]) must mirror the lower four bits ([3:0]).
This makes it irrelevant whether LSB first or MSB first is in
effect. As an example of this mirroring, see the default setting
for 0x000, which mirrors Bit 4 and Bit 3. This sets the long
instruction mode, which is the default and the only mode
supported.
The default for the AD9520 is MSB first.
When LSB first is set by 0x000[1] and 0x000[6], it takes effect
immediately, because it only affects the operation of the serial
control port and does not require that an update be executed.
When MSB first mode is active, the instruction and data bytes
must be written from MSB to LSB. Multibyte data transfers in
MSB first format start with an instruction byte that includes the
register address of the most significant data byte. Subsequent
data bytes must follow in order from the high address to the
low address. In MSB first mode, the serial control port internal
address generator decrements for each data byte of the multibyte
transfer cycle.
When LSB first is active, the instruction and data bytes must be
written from LSB to MSB. Multibyte data transfers in LSB first
format start with an instruction byte that includes the register
address of the least significant data byte followed by multiple
data bytes. In a multibyte transfer cycle, the internal byte
address generator of the serial port increments for each byte.
The AD9520 serial control port register address decrements
from the register address just written toward 0x000 for multibyte
I/O operations if the MSB first mode is active (default). If the
LSB first mode is active, the register address of the serial control
port increments from the address just written toward 0x232 for
multibyte I/O operations.
Streaming mode always terminates when it reaches 0x232. Note
that unused addresses are not skipped during multibyte I/O
operations.
Table 44. Streaming Mode (No Addresses Are Skipped)
Write Mode
LSB first
MSB first
Address Direction
Increment
Decrement
Stop Sequence
0x230, 0x231, 0x232, stop
0x001, 0x000, 0x232, stop
AD9520-3