AD9520-3BCPZ Analog Devices Inc, AD9520-3BCPZ Datasheet - Page 51

• Manufacturer Part Number: AD9520-3BCPZ
• Description: 12/24 Channel Clock Gen 2,0GH
• Manufacturer: Analog Devices Inc
• Type: Clock Generator, Fanout Distributionr

Specifications of AD9520-3BCPZ

• Design Resources: Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers (CN0121) Phase Coherent FSK Modulator (CN0186)
• Pll: Yes
• Input: CMOS, LVDS, LVPECL
• Output: CMOS, LVPECL
• Number Of Circuits: 1
• Ratio - Input:output: 2:12, 2:24
• Differential - Input:output: Yes/Yes
• Frequency - Max: 2.25GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LFCSP
• Frequency-max: 2.25GHz
• Function: Clock Generator
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Package Type: LFCSP EP
• Pin Count: 64
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SERIAL CONTROL PORT
The AD9520 serial control port is a flexible, synchronous serial
communications port that allows an easy interface with many
industry-standard microcontrollers and microprocessors. The
AD9520 serial control port is compatible with most synchronous
transfer formats, including Philips I2C, Motorola® SPI®, and
Intel® SSR protocols. The AD9520 I2C implementation deviates
from the classic I2C specification on two specifications, and
these deviations are documented in Table 14 of this data sheet.
The serial control port allows read/write access to all registers
that configure the AD9520.
SPI/I²C PORT SELECTION
The AD9520 has two serial interfaces, SPI and I2C. Users can
select either SPI or I2C depending on the states of the three
logic level (high, open, low) input pins, SP1 and SP0. When
both SP1 and SP0 are high, the SPI interface is active. Otherwise,
I2C is active with eight different I2C slave address (seven bits
wide) settings, see Table 40. The four MSBs of the slave address
are hardware coded as 1011 and the three LSBs are programmed by
SP1 and SP0.
Table 40. Serial Port Mode Selection
SP1
Low
Low
Low
Open
Open
Open
High
High
High
I²C SERIAL PORT OPERATION
The AD9520 I2C port is based on the I2C fast mode standard.
The AD9520 supports both I2C protocols: standard mode
(100 kHz) and fast mode (400 kHz).
The AD9520 I2C port has a 2-wire interface consisting of a serial
data line (SDA) and a serial clock line (SCL). In an I2C bus system,
the AD9520 is connected to the serial bus (data bus SDA and
clock bus SCL) as a slave device, meaning that no clock is generated
by the AD9520. The AD9520 uses direct 16-bit (2 bytes)
memory addressing instead of traditional 8-bit (1 byte) memory
addressing.
SP0
Low
Open
High
Low
Open
High
Low
Open
High
Address
I²C, 1011001
I²C, 1011010
I²C, 1011011
I²C, 1011100
I²C, 1011101
I²C, 1011110
I²C, 1011111
SPI
I²C, 1011000
Rev. 0 | Page 51 of 84
I
Table 41. I
Abbreviation
S
Sr
P
A
A
W
R
One pulse on the SCL clock line is generated for each data bit
transferred.
The data on the SDA line must not change during the high
period of the clock. The state of the data line can only change when
the clock on the SCL line is low.
SDA
A start condition is a transition from high to low on the SDA
line while SCL is high. The start condition is always generated
by the master to initialize the data transfer.
A stop condition is a transition from low to high on the SDA
line while SCL is high. The stop condition is always generated
by the master to end the data transfer.
SDA
A byte on the SDA line is always 8 bits long. An acknowledge bit
must follow every byte. Bytes are sent MSB first.
The acknowledge bit is the ninth bit attached to any 8-bit data
byte. An acknowledge bit is always generated by the receiving
device (receiver) to inform the transmitter that the byte has
been received. It is done by pulling the SDA line low during the
ninth clock pulse after each 8-bit data byte.
SCL
SCL
2
C Bus Characteristics
CONDITION
START
S
2
C Bus Definitions
DATA VALID
DATA LINE
STABLE;
Figure 56. Start and Stop Conditions
Figure 55. Valid Bit Transfer
Definition
Start
Repeated Start
Stop
Acknowledge
No acknowledge
Write
Read
ALLOWED
OF DATA
CHANGE
AD9520-3
CONDITION
STOP
P