AD9520-3BCPZ Analog Devices Inc, AD9520-3BCPZ Datasheet - Page 56

• Manufacturer Part Number: AD9520-3BCPZ
• Description: 12/24 Channel Clock Gen 2,0GH
• Manufacturer: Analog Devices Inc
• Type: Clock Generator, Fanout Distributionr

Specifications of AD9520-3BCPZ

• Design Resources: Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers (CN0121) Phase Coherent FSK Modulator (CN0186)
• Pll: Yes
• Input: CMOS, LVDS, LVPECL
• Output: CMOS, LVPECL
• Number Of Circuits: 1
• Ratio - Input:output: 2:12, 2:24
• Differential - Input:output: Yes/Yes
• Frequency - Max: 2.25GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LFCSP
• Frequency-max: 2.25GHz
• Function: Clock Generator
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Package Type: LFCSP EP
• Pin Count: 64
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9520-3
Table 45. Serial Control Port, 16-Bit Instruction Word, MSB First
MSB
I15
R/W
SCLK
SCLK
SCLK
SDIO
SDIO
SDIO
SDO
CS
CS
CS
DON'T CARE
DON'T CARE
DON'T CARE
DON'T CARE
DON'T CARE
SCLK
SDIO
CS
DON'T CARE
R/W
I14
W1
DON'T CARE
DON'T CARE
W1
R/W
A0 A1 A2 A3
W0
W1
16-BIT INSTRUCTION HEADER
A12
A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
I13
W0
W0
A12
t
S
R/W
A11 A10 A9 A8 A7
A4
I12
A12 = 0
16-BIT INSTRUCTION HEADER
16-BIT INSTRUCTION HEADER
t
A5 A6 A7 A8
Figure 65. Serial Control Port Write—MSB First, 16-Bit Instruction, Timing Measurements
DS
W1
Figure 63. Serial Control Port Write—MSB First, 16-Bit Instruction, Two Bytes Data
Figure 64. Serial Control Port Read—MSB First, 16-Bit Instruction, Four Bytes Data
Figure 67. Serial Control Port Write—LSB First, 16-Bit Instruction, Two Bytes Data
SCLK
SDIO
SDO
W0
t
CS
DH
I11
A11 = 0
Figure 66. Timing Diagram for Serial Control Port Register Read
A12
A6 A5
A9 A10 A11 A12
t
LOW
A11
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
A4 A3 A2
REGISTER (N) DATA
I10
A10 = 0
DATA BIT N
A10
t
HIGH
W0
t
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DV
A9
A1 A0
W1
t
CLK
I9
A9
R/W
A8
D0
D7 D6 D5 D4 D3
DATA BIT N – 1
REGISTER (N – 1) DATA
I8
A8
A7
D1
REGISTER (N) DATA
REGISTER (N) DATA
D2 D3 D4
I7
A7
A6
A5
I6
A6
D2 D1 D0 D7
D5 D6 D7
D4
I5
REGISTER (N – 2) DATA
A5
D3
D0
I4
A4
D2
D6 D5
REGISTER (N – 1) DATA
D1 D2
REGISTER (N + 1) DATA
I3
A3
D1
D4 D3 D2
D3 D4 D5
REGISTER (N – 3) DATA
D0
I2
A2
t
C
D1 D0
D6
I1
A1
DON'T CARE
DON'T CARE
D7
DON'T CARE
DON'T CARE
I0
A0
DON'T CARE
DON'T CARE
DON'T CARE
DON'T
CARE
LSB