ADUC7020BCPZ62I-RL Analog Devices Inc, ADUC7020BCPZ62I-RL Datasheet - Page 76

• Manufacturer Part Number: ADUC7020BCPZ62I-RL
• Description: IC,MICROCONTROLLER,16-BIT,ARM7 CPU,CMOS,LLCC,40PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC7xxxr

Specifications of ADUC7020BCPZ62I-RL

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 44MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: PLA, PWM, PSM, Temp Sensor, WDT
• Number Of I /o: 14
• Program Memory Size: 62KB (62K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 5x12b; D/A 4x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 40-LFCSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-ADUC7020QSZ - KIT DEV ADUC7020 QUICK STARTEVAL-ADUC7020MKZ - KIT MINI DEV FOR ADUC7026/7027
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADuC7019/20/21/22/24/25/26/27/28/29
Table 146. PLACLK Register
Name
PLACLK
PLACLK is the clock selection for the flip-flops of Block 0 and
Block 1. Note that the maximum frequency when using the
GPIO pins as the clock input for the PLA blocks is 44 MHz.
Table 147. PLACLK MMR Bit Descriptions
Bit
7
6:4
3
2:0
Table 150. Feedback Configuration
Bit
10:9
8:7
Value
000
001
010
011
100
101
Other
000
001
010
011
100
101
Other
Value
00
01
10
11
00
01
10
11
Address
0xFFFF0B40
Description
Reserved.
Block 1 clock source selection.
GPIO clock on P0.5.
GPIO clock on P0.0.
GPIO clock on P0.7.
HCLK.
OCLK (32.768 kHz) external crystal only.
Timer1 overflow.
Reserved.
Reserved.
Block 0 clock source selection.
GPIO clock on P0.5.
GPIO clock on P0.0.
GPIO clock on P0.7.
HCLK.
OCLK (32.768 kHz) external crystal only.
Timer1 overflow.
Reserved.
PLAELM0
Element 15
Element 2
Element 4
Element 6
Element 1
Element 3
Element 5
Element 7
Default Value
0x00
PLAELM1 to PLAELM7
Element 0
Element 2
Element 4
Element 6
Element 1
Element 3
Element 5
Element 7
Access
R/W
Rev. C | Page 76 of 96
Table 148. PLAIRQ Register
Name
PLAIRQ
PLAIRQ enables IRQ0 and/or IRQ1 and selects the source
of the IRQ.
Table 149. PLAIRQ MMR Bit Descriptions
Bit
15:13
12
11:8
7:5
4
3:0
PLAELM8
Element 7
Element 10
Element 12
Element 14
Element 9
Element 11
Element 13
Element 15
Value
0000
0001
1111
0000
0001
1111
Address
0xFFFF0B44
Description
Reserved.
PLA IRQ1 enable bit. Set by user to enable
IRQ1 output from PLA. Cleared by user to
disable IRQ1 output from PLA.
PLA IRQ1 source.
PLA Element 0.
PLA Element 1.
PLA Element 15.
Reserved.
PLA IRQ0 enable bit. Set by user to enable
IRQ0 output from PLA. Cleared by user to
disable IRQ0 output from PLA.
PLA IRQ0 source.
PLA Element 0.
PLA Element 1.
PLA Element 15.
PLAELM9 to PLAELM15
Element 8
Element 10
Element 12
Element 14
Element 9
Element 11
Element 13
Element 15
Default Value
0x00000000
Access
R/W