EP3SL150F780I3N Altera, EP3SL150F780I3N Datasheet - Page 192

• Manufacturer Part Number: EP3SL150F780I3N
• Description: Stratix III
• Manufacturer: Altera

PLLs in Stratix III Devices
Figure 6–29. Automatic Clock Switchover Circuit Block Diagram
6–42
Stratix III Device Handbook, Volume 1
inclk0
inclk1
muxout
■
■
Stratix III device PLLs support a fully configurable clock switchover
capability.
built into the PLL. When the current reference clock is not present, the
clock sense block automatically switches to the backup clock for PLL
reference. The clock switchover circuit also sends out three status
signals—clkbad[0], clkbad[1], and activeclock—from the PLL to
implement a custom switchover circuit in the logic array. You can select
a clock source as the backup clock by connecting it to the inclk1 port of
the PLL in your design.
Automatic Clock Switchover
Use the switchover circuitry to automatically switch between
inclk0/inclk1 when the current reference clock to the PLL stops
toggling. For example, in applications that require a redundant clock with
the same frequency as the reference clock, the switchover state machine
Manual clock switchover: Clock switchover is controlled via the
clkswitch signal in this mode. When the clkswitch signal goes
from logic low to logic high, and stays high for at least three clock
cycles, the reference clock to the PLL is switched from inclk0 to
inclk1, or vice-versa.
Automatic switchover with manual override: This mode combines
Modes 1 and 2. When the clkswitch signal goes high, it overrides
automatic clock switchover mode.
clksw
n Counter
Figure 6–29
Sense
Clock
shows the block diagram of the switchover circuit
refclk
Switchover
Machine
State
Clock Switch
PFD
Control Logic
fbclk
clkbad0
clkbad1
activeclock
clkswitch
Altera Corporation
November 2007