EP3SL150F780I3N Altera, EP3SL150F780I3N Datasheet - Page 278

• Manufacturer Part Number: EP3SL150F780I3N
• Description: Stratix III
• Manufacturer: Altera

Memory Interfaces Pin Support
8–8
Stratix III Device Handbook, Volume 1
Notes to
(1)
(2)
(3)
(4)
×4
×8/×9
×16/×18
×32/×36
Table 8–4. Stratix III DQS/DQ Bus Mode Pins
The QVLD pin is not used in the ALTMEMPHY megafunction.
Two ×4 DQ groups are stitched to make a ×8/×9 group.
Four ×4 DQ groups are stitched to make a ×16/×18 group. Three pins from any of the original ×4 group become
user I/O pins.
Eight ×4 DQ groups are stitched to make a ×32/×36 group. Nine pins from any of the original ×4 group become
user I/O pins.
Mode
(2)
(3)
(4)
Table
8–4:
DQSn Support
Yes
Yes
Yes
Yes
Every I/O bank in the Stratix III device can support DQS and DQ signals
with DQ bus modes of ×4, ×8/×9, ×16/×18, or ×32/×36 although not all
devices support ×16/×18 or ×32/×36 (see
DQS and DQSn pin-pair drives up to four DQ pins within that group.
There is no support for the CQn pin in this mode. In ×8/×9 mode, each
DQS and DQSn/CQn pin-pair drives up to ten DQ pins, to support one
parity bit or DM, eight data bits, and an optional QVLD pin. If the parity
bit, DM bit, QVLD pin, or any data bit is not used, these pins can be used
as regular user I/O pins.
Similarly, with ×16/×18 and ×32/×36 modes, each DQS and DQSn/CQn
pin-pair drives up to 19 and 37 DQ pins, respectively, with the optional
QVLD pin in each group. There are two parity or DM bits (counted in the
number of DQ pins) in the ×16/×18 mode and four parity or DM bits in
the ×32/×36 mode.
DQS/DQ bus mode, including the DQS and DQSn/CQn pin-pair.
CQn Support
Yes
Yes
Yes
No
Table 8–4
Number of Pins
Maximum
per Group
12
21
39
6
lists the maximum number of pins per
Data
16
32
Table
4
8
8–5). In ×4 mode, each
(Optional)
Parity or
DM
—
1
2
4
Altera Corporation
November 2007
(Optional)
QVLD
(1)
—
1
1
1