EP3SL150F780I3N Altera, EP3SL150F780I3N Datasheet - Page 526

• Manufacturer Part Number: EP3SL150F780I3N
• Description: Stratix III
• Manufacturer: Altera

Switching Characteristics
Switching
Characteristics
1–14
Stratix III Device Handbook, Volume 2
EP3SL50
EP3SL70
Table 1–17. Stratix III Clock Tree Performance (Part 1 of 2)
Device
f
V
C C L
-2 Speed
Grade
600
600
= 1.1V
See
the EPE and PowerPlay Power Analyzer for current estimates of
remaining power supplies.
For more information about power estimation tools, refer to the Early
Power Estimator User Guide and the PowerPlay Power Analysis chapters in
the Quartus II Handbook.
This section provides performance characteristics of Stratix III core and
periphery blocks for commercial grade devices.
These characteristics can be designated as Preliminary and Final and
each designation is defined below.
Preliminary
Preliminary characteristics are created using simulation results, process
data, and other known parameters.
Final
Final numbers are based on actual silicon characterization and testing.
These numbers reflect the actual performance of the device under worst-
case silicon process, voltage and junction temperature conditions. The
upper-right hand corner of a table shows the designation as Preliminary
or Final.
Core Performance Specifications
This sections describes the Clock Tree, PLL, DSP, TriMatrix, and
Configuration and JTAG Specifications.
Clock Tree Specifications
Table 1–17
array, DSP blocks, and TriMatrix Memory blocks for Stratix III devices.
V
Table 1–4
C C L
-3 Speed
Grade
500
500
= 1.1V
lists the clock tree performance specifications for the logic
for supply current estimates for V
V
C C L
-4 Speed
Grade
450
450
= 1.1V
V
C C L
450
450
= 1.1V
-4L Speed
Grade
CCPGM
V
and V
C C L
Altera Corporation
375
375
= 0.9V
November 2007
CC_CLKIN
Preliminary
MHz
MHz
Unit
. Use