EP3SL150F780I3N Altera, EP3SL150F780I3N Datasheet - Page 31

• Manufacturer Part Number: EP3SL150F780I3N
• Description: Stratix III
• Manufacturer: Altera

Altera Corporation
November 2007
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The design security feature is available when configuring Stratix III
FPGAs using the fast passive parallel (FPP) configuration mode with an
external host (such as a MAX II device or microprocessor), or when using
fast active serial (AS) or passive serial (PS) configuration schemes.
For more information on the design security feature, refer to the
Security in Stratix III Devices
Handbook.
SEU Mitigation
Stratix III devices have built-in error detection circuitry to detect data
corruption due to soft errors in the configuration random-access memory
(CRAM) cells. This feature allows all CRAM contents to be read and
verified continuously during user mode operation to match a
configuration-computed CRC value. The enhanced CRC circuit and
frame-based configuration architecture allows detection and location of
multiple, single, and adjacent bit errors which, in conjunction with a soft
circuit supplied as a reference design, allows don't-care soft errors in the
CRAM to be ignored during device operation. This provides a step
decrease in the effective soft error rate, increasing system reliability.
On-chip memory block SEU mitigation is also offered using the 9
a configurable Megafunction in Quartus II for MLAB and M9K blocks
while the M144K memory blocks have built-in error correction code
(ECC) circuitry.
For more information on the dedicated error detection circuitry, refer to
the
Stratix III Device Handbook.
Programmable Power
Stratix III delivers Programmable Power, the only FPGA with user
programmable power options balancing today's power and performance
requirements. Stratix III devices utilize the most advanced power saving
techniques including a variety of process, circuit, and architecture
optimizations and innovations. In addition, user controllable power
reduction techniques provide an optimal balance of performance and
power reduction specific for each design configured into the Stratix III
FPGA. The Quartus II software (starting from Version 6.1) automatically
optimizes designs to meet the performance goals while simultaneously
leveraging the programmable power saving options available in the
Stratix III FPGA without the need for any changes to the design flow.
SEU Mitigation in Stratix III Devices
chapter in volume 1 of the Stratix III Device
Stratix III Device Handbook, Volume 1
chapter in volume 1 of the
Stratix III Device Family Overview
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Design
bit and
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