EP3SL150F780I3N Altera, EP3SL150F780I3N Datasheet - Page 219

• Manufacturer Part Number: EP3SL150F780I3N
• Description: Stratix III
• Manufacturer: Altera

Introduction
Stratix III
I/O Standards
Support
Altera Corporation
November 2007
SIII51007-1.3
Stratix
integration while simultaneously providing the high bandwidth required
to maximize internal logic capabilities and produce system-level
performance. Independent modular I/O banks with a common bank
structure for vertical migration lend efficiency and flexibility to the high
speed I/O. Package and die enhancements with dynamic termination
and output control provide best-in-class signal integrity. Numerous I/O
features assist in high-speed data transfer into and out of the device,
including:
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Stratix III devices support a wide range of industry I/O standards.
Table 7–1
the typical applications. Stratix III devices support a V
of 3.3, 3.0, 2.5, 1.8, 1.5, and 1.2 V.
Single-ended, non-voltage-referenced and voltage-referenced I/O
standards
Low-voltage differential signaling (LVDS), reduced swing
differential signal (RSDS), mini-LVDS, high-speed transceiver logic
(HSTL), and stub series terminated logic (SSTL)
Single data rate (SDR) and half data rate (HDR - half frequency and
twice data width of SDR) input and output options
Up to 132 full duplex 1.25 Gbps true LVDS channels (132 Tx + 132 Rx)
on the row I/O banks
Hard DPA block with serializer/deserializer (SERDES)
De-skew, read and write leveling, and clock-domain crossing
functionality
Programmable output current strength
Programmable slew rate
Programmable delay
Programmable bus-hold
Programmable pull-up resistor
Open-drain output
Serial, parallel, and dynamic on-chip termination (OCT)
Differential OCT
Programmable pre-emphasis
Programmable differential output voltage (VOD)
®
III I/Os are specifically designed for ease of use and rapid system
shows the I/O standards Stratix III devices support as well as
7. Stratix III Device I/O
CCIO
Features
voltage level
7–1