EP3SL150F780I3N Altera, EP3SL150F780I3N Datasheet - Page 785

• Manufacturer Part Number: EP3SL150F780I3N
• Description: Stratix III
• Manufacturer: Altera

Altera Corporation
November 2007
RCLK output adder
RCLK PLL output adder
3.3-V
LVTTL
3.3-V
LVCMOS
3.0-V
LVTTL
3.0-V
LVCMOS
Standard
Table 1–114. EP3SE50 Row Pin Delay Adders for Regional Clock
Table 1–115. EP3SE80 Column Pins Input Timing Parameters (Part 1 of 4)
I/O
Parameter
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
GCLK
Clock
PLL
PLL
PLL
PLL
Parameter
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Industrial Commercial V
SU
SU
SU
SU
SU
SU
SU
SU
H
H
H
H
H
H
H
H
—
—
EP3SE80 I/O Timing Parameters
Table 1–115
parameters for EP3SE80 devices for single-ended I/O standards.
Table 1–115
single-ended I/O standards.
Fast Model
Industrial Commercial
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
-0.053
Fast Model
0.0
specifies EP3SE80 Column Pins Input Timing parameters for
through
Stratix III Device Datasheet: DC and Switching Characteristics
-0.981
-0.364
-0.981
-0.364
-0.981
-0.364
-0.981
-0.364
1.089
0.472
1.089
0.472
1.089
0.472
1.089
0.472
Table 1–118
CCL
0.077
0.003
-2
=1.1V V
-1.425 -1.522 -1.638 -1.577 -1.964
-0.721 -0.850 -0.970 -0.913 -0.838
-1.425 -1.522 -1.638 -1.577 -1.964
-0.721 -0.850 -0.970 -0.913 -0.838
-1.425 -1.522 -1.638 -1.577 -1.964
-0.721 -0.850 -0.970 -0.913 -0.838
-1.425 -1.522 -1.638 -1.577 -1.964
-0.721 -0.850 -0.970 -0.913 -0.838
V
1.567
0.863
1.567
0.863
1.567
0.863
1.567
0.863
1.1V
CCL
-2
=
CCL
show the maximum I/O timing
0.269
0.074
-3
=1.1V V
V
1.683
1.011
1.683
1.011
1.683
1.011
1.683
1.011
1.1V
Stratix III Device Handbook, Volume 2
CCL
-3
=
CCL
1.813
1.145
1.813
1.145
1.813
1.145
1.813
1.145
V
1.1V
0.151
0.37
CCL
-4
-4
=1.1V V
=
1.744
1.080
1.744
1.080
1.744
1.080
1.744
1.080
V
1.1V
CCL
CCL
=
0.327
0.115
-4L
=1.1V V
V
2.125
0.999
2.125
0.999
2.125
0.999
2.125
0.999
0.9V
CCL
-4L
=
CCL
0.566
0.359
Units
1–273
=0.9V
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Units
ns
ns