EP3SL150F780I3N Altera, EP3SL150F780I3N Datasheet - Page 38

• Manufacturer Part Number: EP3SL150F780I3N
• Description: Stratix III
• Manufacturer: Altera

Logic Array Blocks
Figure 2–3. Direct Link Connection
2–4
Stratix III Device Handbook, Volume 1
Direct link
interconnect
to left
block, DSP block, or IOE output
ALMs
Direct link interconnect from
left LAB, TriMatrix memory
MLAB
Figure 2–3
LAB Control Signals
Each LAB contains dedicated logic for driving control signals to its
ALMs. The control signals include three clocks, three clock enables, two
asynchronous clears, a synchronous clear, and synchronous load control
signals. This gives a maximum of 10 a control signals at a time. Although
you generally use synchronous load and clear signals when
implementing counters, you can also use them with other functions.
Each LAB has two unique clock sources and three clock enable signals, as
shown in
clocks using the two clock sources and three clock enable signals. Each
LAB's clock and clock enable signals are linked. For example, any ALM
in a particular LAB using the labclk1 signal also uses labclkena1
signal. If the LAB uses both the rising and falling edges of a clock, it also
uses two LAB-wide clock signals. De-asserting the clock enable signal
turns off the corresponding LAB-wide clock.
Interconnect
Local
Figure
shows the direct link connection.
2–4. The LAB control block can generate up to three
LAB
ALMs
Direct link
interconnect
to right
Direct link interconnect from
right LAB, TriMatrix memory
block, DSP block, or IOE output
Altera Corporation
October 2007