EP3SL150F780I3N Altera, EP3SL150F780I3N Datasheet - Page 205

• Manufacturer Part Number: EP3SL150F780I3N
• Description: Stratix III
• Manufacturer: Altera

Figure 6–38. PLL Reconfiguration Waveform
Altera Corporation
November 2007
CONFIGUPDATE
SCANDATAOUT
SCANCLKENA
SCANDONE
SCANDATA
SCANCLK
ARESET
Dn_old
Dn
Figure 6–38
feature.
1
Post-Scale Counters (C0 to C9)
The multiply or divide values and duty cycle of post-scale counters can
be reconfigured in real time. Each counter has an 8-bit high-time setting
and an 8-bit low-time setting. The duty cycle is the ratio of output
high- or low-time to the total cycle time, which is the sum of the two.
Additionally, these counters have two control bits, rbypass, for
bypassing the counter, and rselodd, to select the output clock duty
cycle.
When the rbypass bit is set to 1, it bypasses the counter, resulting in a
divide by 1. When this bit is set to 0, the high- and low-time counters are
added to compute the effective division of the VCO output frequency. For
example, if the post-scale divide factor is 10, the high- and low-count
values could be set to 5 and 5, respectively, to achieve a 50-50% duty
cycle. The PLL implements this duty cycle by transitioning the output
When you reconfigure the counter clock frequency, you cannot
reconfigure the corresponding counter phase shift settings using
the same interface. Instead, reconfigure the phase shifts in real
time using the dynamic phase shift reconfiguration interface. If
you reconfigure the counter frequency, but wish to keep the
same non-zero phase shift setting (for example, 90 degrees) on
the clock output, you must reconfigure the phase shift
immediately after reconfiguring the counter clock frequency.
shows a functional simulation of the PLL reconfiguration
Clock Networks and PLLs in Stratix III Devices
Stratix III Device Handbook, Volume 1
D0_old
D0
Dn
6–55