EP3SL150F780I3N Altera, EP3SL150F780I3N Datasheet - Page 36

• Manufacturer Part Number: EP3SL150F780I3N
• Description: Stratix III
• Manufacturer: Altera

Logic Array Blocks
Figure 2–1. Stratix III LAB Structure
2–2
Stratix III Device Handbook, Volume 1
Direct link
interconnect from
adjacent block
Direct link
interconnect to
adjacent block
R20
R4
f
Local Interconnect
The LAB of Stratix III has a new derivative called Memory LAB (MLAB),
which adds look-up table (LUT)-based SRAM capability to the LAB as
shown in
simple dual-port static random access memory (SRAM). You can
configure each ALM in an MLAB as either a 64
resulting in a configuration of 64
block. MLAB and LAB blocks always co-exist as pairs in all Stratix III
families. MLAB is a superset of the LAB and includes all LAB features.
Figure 2–2
The MLAB is described in detail in the
in Stratix III Devices
Figure
shows an overview of LAB and MLAB topology.
LAB
2–2. The MLAB supports a maximum of 640-bits of
chapter in volume 1 of the Stratix III Device Handbook.
C4
from Either Side by Columns & LABs,
C12
Local Interconnect is Driven
& from Above by Rows
Row Interconnects of
Variable Speed & Length
×
10 or 32
TriMatrix Embedded Memory Blocks
MLAB
×
20 simple dual port SRAM
ALMs
×
1 or 32
Column Interconnects of
Variable Speed & Length
Altera Corporation
×
2 block,
October 2007
Direct link
interconnect from
adjacent block
Direct link
interconnect to
adjacent block