TMC2072-MD SMSC, TMC2072-MD Datasheet - Page 43

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TMC2072-MD

Manufacturer Part Number
TMC2072-MD
Description
Network Controller & Processor ICs Peripheral Mode CircLink Cntlr
Manufacturer
SMSC
Datasheet

Specifications of TMC2072-MD

Product
Controller Area Network (CAN)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Peripheral Mode CircLink™ Controller
Datasheet
2.9.2
SMSC TMC2072
1 Clear FRCV Bit
2 Release Interrupt Mask
3 Write Receive Flag
4 Read EC Status
5 Read Receive Flag
6 Read Packet
7 Interrupt Mask
CPU Side
( ): it is FBE, PAC addressed to a self
Example of Receive Flow in Free Format Mode
(RXMH/RXML REGISTER: When in RXM07 = 0)
A CPU controls a series of sequences such as "Issuing RX CMD → Handling interrupt after RX → Packet
read".
After the receive completion in the free format mode, the FRCV (Free format receive end flag) in the EC
interruption status register (INTSTA) changes from 0 to 1, permitting the flag to be an interrupt source.
DATASHEET
Page 43
FRCV,RXF07 = 0->1
Interrupt occure
RXF07 = 1->0
FRCV = 1->0
TMC2074/72
(ACK)
(ACK)
Revision 0.1 (06-07-07)
LAN Side
FBE
PAC [SID=07h]

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