TMC2072-MD SMSC, TMC2072-MD Datasheet - Page 49

• Manufacturer Part Number: TMC2072-MD
• Description: Network Controller & Processor ICs Peripheral Mode CircLink Cntlr
• Manufacturer: SMSC

Specifications of TMC2072-MD

• Product: Controller Area Network (CAN)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Peripheral Mode CircLink™ Controller
Datasheet
2.11.2 Time-Synchronous Sequence
Supplement:
SMSC TMC2072
Time readout
Accessing the NST register can dynamically provide the latest time data. Since NST is a 16 bit wide
counter, it is necessary to read the even address side (10h) first when an 8-bit bus is used. When the even
address is read out, the remaining 8 bits of the NST are latched internally.
CM and CS nodes
To synchronize NST, one clock master (CM) should be designated on the network. The other nodes
become clock slave nodes (CS node). The clock master ID (CMID) must be set in the CMID register of
every node. All nodes on the network set the same value as CMID.
CM node
CMID equals to its node ID
Only one node on the network
Counting NST and notifying the CS nodes of the NST by sending packets.
CS node
CMID not equals to its node ID
Receiving a packet from the node specified by CMID and synchronizing NST with its own clock.
Preset at first receive
The NST of each node starts counting as free run immediately after power-up. CS nodes preset the
received NST as the NST of its own after receiving the first packet from the CM node. This preset
operation is performed only once for the first receive.
The preset operation is performed not only after power-up but also immediately after resetting NSTSTOP
in the MODE register from 1 to 0, after writing CMID register, and after software reset.
Phase tracking after second receive
The CS nodes that are preset by the first receive from the CM node switch into the time synchronization
mode by PLL.
The CS nodes that switch into PLL operation keep comparing their NST to the received NST at every
receive from the CM node. If the phase is different, the CS nodes dynamically control the speed of their
counter to let the phase follow the NST in the CM node.
When the difference count value between the receiver’s NST and the received NST from CM node,
is +2 and above, the receiver’s counter is slowed to compensate. When the difference is –1 and
below, the receiver’s counter is speeded up. When the difference is 0 or +1, the local counter
makes no adjustment.
DATASHEET
Page 49
Revision 0.1 (06-07-07)