TMC2072-MD SMSC, TMC2072-MD Datasheet - Page 76

• Manufacturer Part Number: TMC2072-MD
• Description: Network Controller & Processor ICs Peripheral Mode CircLink Cntlr
• Manufacturer: SMSC

Specifications of TMC2072-MD

• Product: Controller Area Network (CAN)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Peripheral Mode CircLink™ Controller
Datasheet
The upper 8 bits indicate the receive status, and the lower 8 bits indicate the send status. Every bit in this
register can be used to generate an interrupt .
RXERR (bit 15)
This bit indicates that receive has stopped due to an error during packet receive. As soon as this bit is set,
the details of the error are reflected to RXEC 2-0 (bits 7 to 5) in the ERRINFO register, and the ID of the
sending node is stored to RESID 4-0 (bits 4 to 0) in the same register. Note that this bit is not set by any
message other than a packet (Token, FBE, ACK, or NAK).
This bit is cleared by 1 writing or by a software reset.
CMIECC (bit 14)
This bit indicates that error correction of received data has been performed in the CMI decoding circuit. As
soon as this bit is set, the details of error are stored in CMIEI3-0 (bits 11 to 8) of the ERRINFO register.
This bit is cleared by writing a 1 or by software reset.
NSTUNLOC (bit 13)
Indicates synchronizing with the CM node’s NST. This bit is set by Software Reset. For further details,
please refer to section 2.11.
0: Synchronous Lock status 1: Synchronous Unlock Status (Initial Value)
In the CM node, this flag goes into steady state 0 (Synchronous Lock status). Accordingly, the initial
settings are as seen below.
In Peripheral mode, the CM node ID is set in a register after cancellation of Hardware Reset. After these
values are imported, the output is 1 until it assumes itself as a CM node (it becomes 0 after that). During
Software Reset, due to the CM Node ID being immediately imported, the CM Node ID is fixed at 1→0
immediately after set-up in the register.
WARTERR (bit 12)
This bit is set if data is not received by any page set in remote buffer receive mode within a fixed period.
This bit is cleared by the WARTERR clear command or by a software reset.
1: No receive within a fixed period, 0: Receive within a fixed period.
FRCV (bit 11)
This bit is set if the reception by any page set in free format receive mode is completed normally. This bit is
cleared by writing a 1 or by a software reset.
1: Receive complete, 0: Receive in progress
RRCV (bit 10)
This bit is set if the reception of any page set in remote buffer receive mode is completed normally. This bit
is cleared by writing a 1 or by a software reset.
1: Receive complete, 0: Receive in progress
MRCV (bit 9)
Revision 0.1 (06-07-07)
Page 76
SMSC TMC2072
DATASHEET