TMC2072-MD SMSC, TMC2072-MD Datasheet - Page 67

• Manufacturer Part Number: TMC2072-MD
• Description: Network Controller & Processor ICs Peripheral Mode CircLink Cntlr
• Manufacturer: SMSC

Specifications of TMC2072-MD

• Product: Controller Area Network (CAN)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Peripheral Mode CircLink™ Controller
Datasheet
3.2.3
SMSC TMC2072
COMR2 Register: Page Register
*1: Not equivalent to the ARCNET original specifications. (Bit length variable)
- When reading/writing: ARCNET address pointer upper register (New)
RDDATA (bit 7)
This bit specifies the type of access to data register (COMR4) handled.
1: Reading from data register
0: Write to data register
AUTOINC (bit 6)
This specifies an automatic increment mode of the RAMADR accessing data register (COMR4). The
incremental value is +1 for 8 bits bus width and 0 word mode (W16 = L, WDMD = 0), and +2 for 8 bits bus
width and 1 word mode (W16=L, WDMD=1) or 16 bits bus width (W16=1).
1: Automatically incremented
0: Not automatically incremented
nWRAPAR (bit 5)
This bit specifies internal operation mode when the most significant bit (MSB) of RAMADR is carried over.
1: Move to the top of the next page
0: Go back to the top of the current page
PAGE 4-0 (bits 4 to 0)
These bits specify the page numbers of the packet buffers. Rewriting these 5 bits is not valid before
address in the page (COMR3) is written. Note that the upper limit of specifiable value is restricted by the
page size and unnecessary higher bits in CircLink are deleted.
*1
*1
COMR2
[READ/WRITE]
15-8
4-0
bit
7
6
5
(Page Register)
name
--------
RDDATA
AUTOINC
nWRAPAR
PAGE4-0
DATASHEET
init. value
X
X
X
0
0
Page 67
description
reserved (all "0")
Read Data
Auto Increment
Wrap-around mode
Page 4-0
address:04h
Revision 0.1 (06-07-07)