TMC2072-MD SMSC, TMC2072-MD Datasheet - Page 63

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TMC2072-MD

Manufacturer Part Number
TMC2072-MD
Description
Network Controller & Processor ICs Peripheral Mode CircLink Cntlr
Manufacturer
SMSC
Datasheet

Specifications of TMC2072-MD

Product
Controller Area Network (CAN)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Peripheral Mode CircLink™ Controller
Datasheet
3.2
3.2.1
SMSC TMC2072
Register Details
COMR0 Register: Status/interrupt Mask Register
- When reading: ARCNET status register
POR (bit 4)
When this bit is 1, it indicates that a hardware or software reset has been occurred?. This bit can be
cleared by writing the POR clear command (0Eh).
RECON (bit 2)
When this bit is 1 it indicates that a reconfiguration has occurred. This bit can be cleared by software reset
or by writing the RECON clear command (16h).
TMA (bit 1)
When this bit is 1, it indicates that a transmission has been performed correctly (except broadcast
messages). This bit is valid only after the TA bit has been set to 1 and can be cleared by a software reset
or by writing the send command (03h).
TA (bit 0)
When this bit is 1, it indicates that sending is complete, and 0 indicates that sending is in progress. This bit
becomes 0 when a write or send command (03h) is executed. In the case of free buffer mode (TXM = 0) or
*1 Not equivalent to the ARCNET original specifications.
*1
*1
*1
COMR0
[READ]
COMR0
[WRITE]
15-8
15-8
6,5
6-4
bit
bit
7
4
3
2
1
0
7
3
2
1
0
(Status Register)
name
--------
--------
--------
POR
--------
RECON
TMA
TA
(Mask Register)
name
--------
--------
--------
EXCNAK
RECON
NXTIDERR
TA
DATASHEET
init. value
init. value
0,0,0
1,1
0
1
1
0
0
0
1
0
0
0
0
0
0
Page 63
Description
reserved (all "0")
reserved
reserved
Power On Reset
reserved
Reconfiguration
Transmitter Message Acknowledged
Transmitter Available
description
reserved (all "0")
reserved ("0")
reserved (all "0")
Excessive NAK
Reconfiguration
Next ID Error
Transmitter Available
address:00h
address:00h
Revision 0.1 (06-07-07)

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