TMC2072-MD SMSC, TMC2072-MD Datasheet - Page 77

• Manufacturer Part Number: TMC2072-MD
• Description: Network Controller & Processor ICs Peripheral Mode CircLink Cntlr
• Manufacturer: SMSC

Specifications of TMC2072-MD

• Product: Controller Area Network (CAN)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Peripheral Mode CircLink™ Controller
Datasheet
SMSC TMC2072
This bit is set if receive of a packet sent to the local node is completed normally. This bit is cleared by
writing a 1 or by a software reset.
1: Receive complete, 0: Receive in progress
SIDF (bit 8)
This bit is set if a packet sent from the SID specified by the SSID register is received. This bit is cleared by
writing a 1or by a software reset.
TKNRETF (bit 7)
This bit indicates that a token retry is performed. Refer to section 2.4.1 - Reducing Token Loss for details.
This bit is cleared by writing a 1or by a software reset.
ACKNAKF (bit 6)
This bit indicates that countermeasures corrupt ACK/NAK data have been implemented. Refer to section
2.4.1 - Reducing Token Loss for details. This bit is cleared by writing a 1 or by a software reset.
HUBWDTO (bit 5)
This bit indicates that the HUB unit has been reset which was caused by timeout of watchdog timer,. This
is done to prevent the direction control circuit of the HUB unit from hanging-up. A timeout occurs if the
transmit signal from HUB is continuously active for 3.27 ms or more. (when using 2.5 Mbps. At 5 Mbps, the
value is half -> 1.64ms)
This timeout causes the HUB unit and two CMI units to be automatically reset. (If the HUB unit is OFF, the
CMI units are not reset.) This bit is cleared by writing a 1or by a software reset.
CPERR (bit 4)
This bit is set if the CP field of the preceding packet is of a value that exceeded the page boundary, or is
between 00h and 02h, both of which are invalid CP settings.
Refer to section 2.5.3 - Packet Data Structure for details. This bit is cleared by writing a 1 or by a software
reset.
1: Packet including invalid CP field is sent, 0: Normal packet is sent
COM (bit 3)
This bit is set to 1 if there is an interrupt from the ARCNET core. Be sure to set the bit of COMR0 mask
register bits when required.
This bit is set to 1 when the interrupt is generated by EXCNAK, RECON, NXTIDERR and TA bit in the
mask register of COMR0.
FBENR (bit 2)
Both FBENR and TXERR bits are set if there is no response to FBE . If this bit is set, it is possible to
determine that data is transmitted to a node that would not cause a sending failure, thus identifying failures
based on deformed packet data. This bit is cleared by writing a 1, issuing send command, , or by a
software reset.
TXERR (bit 1)
DATASHEET
Page 77
Revision 0.1 (06-07-07)