FDMA510PZ Fairchild Semiconductor, FDMA510PZ Datasheet - Page 4

• Manufacturer Part Number: FDMA510PZ
• Description: MOSFET P-CH 20V 7.8A 6-MICROFET
• Manufacturer: Fairchild Semiconductor
• Series: PowerTrench®r
• Type: Power MOSFETr

Specifications of FDMA510PZ

• Fet Type: MOSFET P-Channel, Metal Oxide
• Fet Feature: Logic Level Gate
• Rds On (max) @ Id, Vgs: 30 mOhm @ 7.8A, 4.5V
• Drain To Source Voltage (vdss): 20V
• Current - Continuous Drain (id) @ 25° C: 7.8A
• Vgs(th) (max) @ Id: 1.5V @ 250µA
• Gate Charge (qg) @ Vgs: 27nC @ 4.5V
• Input Capacitance (ciss) @ Vds: 1480pF @ 10V
• Power - Max: 900mW
• Mounting Type: Surface Mount
• Package / Case: 6-MLP, 6-MicroFET™
• Configuration: Single Quad Drain
• Transistor Polarity: P-Channel
• Resistance Drain-source Rds (on): 0.03 Ohm @ 4.5 V
• Drain-source Breakdown Voltage: 20 V
• Gate-source Breakdown Voltage: +/- 8 V
• Continuous Drain Current: 7.8 A
• Power Dissipation: 2400 mW
• Maximum Operating Temperature: + 150 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 55 C
• Number Of Elements: 1
• Polarity: P
• Channel Mode: Enhancement
• Drain-source On-res: 0.03Ohm
• Drain-source On-volt: 20V
• Gate-source Voltage (max): ±8V
• Operating Temp Range: -55C to 150C
• Operating Temperature Classification: Military
• Mounting: Surface Mount
• Pin Count: 6
• Package Type: MicroFET
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: FDMA510PZTR

©2009 Fairchild Semiconductor Corporation
FDMA510PZ Rev.B2
Typical Characteristics
Figure 9.
10
4.5
3.0
1.5
0.0
10
10
10
10
10
10
10
10
10
Figure 7.
-10
100
-1
-2
-3
-4
-5
-6
-7
-8
-9
400
0.5
10
0
0
10
1
-4
V
I
D
DS
= -7.8A
= 0V
Gate Leakage Current vs Gate to
-V
Gate Charge Characteristics
3
GS ,
Source Voltage
5
Q
GATE TO SOURCE VOLTAGE (V)
V
T
g
DD
J
, GATE CHARGE(nC)
10
= 125
= -3V
-3
6
o
C
Figure 11. Single Pulse Maximum Power Dissipation
V
10
DD
T
= -7V
T
J
J
= 25
9
= 25°C unless otherwise noted
V
DD
o
C
10
= -5V
-2
15
12
t, PULSE WIDTH (s)
20
15
10
-1
4
0.01
1000
10
3000
0.1
10
100
30
1
0
0.1
0.1
THIS AREA IS
LIMITED BY r
Figure 8.
SINGLE PULSE
T
R
T
Figure 10. Forward Bias Safe
J
A
JA
= MAX RATED
= 25
f = 1MHz
V
GS
= 145
-V
o
-V
= 0V
C
DS
to Source Voltage
DS
o
C/W
, DRAIN to SOURCE VOLTAGE (V)
Operating Area
10
, DRAIN TO SOURCE VOLTAGE (V)
DS(on)
Capacitance vs Drain
1
1
1
SINGLE PULSE
R
T
A
JA
10
V
= 25
GS
= 145
2
o
= -4.5V
C
10
o
C
C
C
C/W
oss
iss
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100ms
100us
10ms
10
1ms
1s
10s
DC
10
3
20
60