SAA7115HLBE NXP Semiconductors, SAA7115HLBE Datasheet - Page 133

• Manufacturer Part Number: SAA7115HLBE
• Description: Video ICs ADV DGTL VIDEO DECODR
• Manufacturer: NXP Semiconductors

Specifications of SAA7115HLBE

• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 70 C
• Package / Case: SOT-407
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Number Of Channels: 2
• Resolution: 8 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: SAA7115HL/V1,557 SAF7115HLBE

Philips Semiconductors
7.18
The frame timing for 525/60 and 625/50 timing cases is
shown pictorially in
tions are used.
7.18.1
The recommended values for the various fields of the
timing registers are shown in
625/50 timing cases. The FREQUENCY field value
shown is for 27 MHz assuming a DSPCPU clock of
143 MHz.
Table 7-11. Timing register recommended values
7.18.2
In data-streaming and message-passing modes, the
EVO
VO_DATA[7:0] lines at rates up to 81 MHz.
Note: In the PNX1300, the data-rate is limited to an 81-
MHz EVO clock.
Data is read from SDRAM in packed form (four 8-bit
bytes per 32-bit word). No data selection or data interpre-
tation is done, and data is transferred at one byte per
VO_CLK from successive byte addresses.
Note: Unused bits of the EVO MMIO registers must be
set to 0 when operating in data transfer modes.
Data-Streaming Mode. In data-streaming mode, data is
stored in SDRAM in two buffers.
When the EVO has transferred out the contents of one
buffer, it interrupts the DSPCPU and begins transferring
out the contents of the second buffer. The DSPCPU sup-
plies pointers to both buffers. The EVO can provide a
continuous stream of data to the EVO output if the
DSPCPU updates the pointer to the next buffer before
the EVO starts transferring data from the next table.
VO_CLOCK FREQUENCY
VO_FRAME FRAME_LENGTH
VO_FIELD
VO_LINE
VO_IMAGE
Register
supplies
FRAME AND FIELD TIMING CONTROL
Recommended values for timing registers
Data-transfer Modes
FIELD_2_START
FRAME_PRESET
F1_VIDEO_LINE
F2_VIDEO_LINE
F1_OLAP
F2_OLAP
FRAME_WIDTH
VIDEO_PIXEL_STAR
T
IMAGE_HEIGHT
IMAGE_WIDTH
a
Figure
Field
stream
7-31. CCIR 656 line defini-
Table 7-11
of
8-bit
525/60
0x855E,
Value
E191
525
264
283
858
138
240
720
20
1
2
3
for 525/60 and
data
(704 visible)
–2 (0xE)
625/50
0x855E,
Value
E191
to
625
336
864
144
288
720
311
23
1
2
the
Note: In this mode, SYNC_MASTER must be set to en-
sure correct operation of VO_IO1 and VO_IO2 as out-
puts.
When each buffer has been transferred, the correspond-
ing buffer-empty bit is set in the status register, and the
DSPCPU is interrupted if the buffer-empty interrupt is en-
abled. To maintain continuous transfer of data, the
DSPCPU supplies new pointers for the next data buffer
following each buffer-empty interrupt. If the DSPCPU
does not supply new pointers before the next field, the
URUN bit is set, and the EVO uses the same pointer val-
ues until they are updated.
When
EVO_ENABLE = 1 and SYNC_STREAMING = 1, the
VO_IO2 signal indicates a data-valid condition. This sig-
nal is asserted when the EVO starts outputting valid data
(that is, data-streaming mode is enabled and video out-
put is running) and is de-asserted when data-streaming
mode is disabled. The VO_IO1 signal generates a pulse
one VO_CLK cycle before the first valid data is sent. See
Section 7.11
Message-Passing Mode. In message-passing mode
data is stored in SDRAM in one buffer.
Note: In this mode, SYNC_MASTER must be set to en-
sure correct operation of VO_IO1 and VO_IO2 as out-
puts.
When message passing is started by setting VO_CTL.
VO_ENABLE, the EVO sends a Start condition on
VO_IO1. When the EVO has transferred the contents of
the buffer, it sends an End condition on VO_IO2 as
shown in
rupts the DSPCPU. The EVO stops, and no further oper-
ation takes place until the DSPCPU sets VO_ENABLE
again to start another message, or until the DSCPU ini-
tiates other EVO operation. See
signal details.
7.18.3
The EVO has five interrupt conditions defined by bits in
the
BFR2_EMPTY, HBE, URUN, and YTR. Each of these
conditions has a corresponding interrupt enable flag and
interrupt acknowledge bit in the VO_CTL register.
The EVO asserts a SOURCE 10 interrupt request to the
PNX1300 vectored interrupt controller as long as one or
more enabled events is asserted.
Note: The interrupt controller should always be pro-
grammed such that the EVO interrupt operates in level-
triggered mode. This ensures that no EVO events can be
lost to the interrupt handler. Refer to
and NMI (Maskable and Non-Maskable Interrupts),”
a description of setting level-triggered mode, as well as
for recommendations on writing interrupt handlers.
The BFR1_EMPTY, BFR2_EMPTY and YTR status
flags indicate to the DSPCPU that a buffer has been
emptied or that the Y threshold has been reached.
The buffer-underrun (URUN) status flag indicates that
the DSPCPU did not acknowledge a BFR1_EMPTY or
PRELIMINARY SPECIFICATION
VO_STATUS
data-streaming
Interrupts and Error Conditions
Figure
for timing signal details.
7-18, sets BFR1_EMPTY, and inter-
register:
mode
Enhanced Video Out
Section 7.11
is
Section 3.5.3, “INT
BFR1_EMPTY,
enabled
for timing
7-23
and
for