SAA7115HLBE NXP Semiconductors, SAA7115HLBE Datasheet - Page 174

• Manufacturer Part Number: SAA7115HLBE
• Description: Video ICs ADV DGTL VIDEO DECODR
• Manufacturer: NXP Semiconductors

Specifications of SAA7115HLBE

• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 70 C
• Package / Case: SOT-407
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Number Of Channels: 2
• Resolution: 8 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: SAA7115HL/V1,557 SAF7115HLBE

PNX1300/01/02/11 Data Book
more details. This shadow copy provides MMIO-space
access to this register. The P,T and M bitfields of this
MMIO register are read-only.
11.6.3
The DRAM_BASE and MMIO_BASE registers are not
normally written through MMIO; their value is determined
by the boot process. Though not recommended, the reg-
isters are writable in MMIO. Special care should be exer-
cised when writing these registers:
Figure 11-8. PCI interface registers accessible in MMIO address space.
11-10
MMIO_base
0x10 300C
0x10 301C
0x10 302C
0x10 3004
0x10 3008
0x10 3010
0x10 3014
0x10 3018
0x10 3020
0x10 3024
0x10 3028
0x10 3030
0x10 3034
0x10 3038
0x10 0000
0x10 0400
offset:
MMIO/DRAM_BASE updates
BIU_STATUS (r/w)
BIU_CTL (r/w)
PCI_ADR (r/w)
PCI_DATA (r/w)
CONFIG_ADR (r/w)
CONFIG_DATA (r/w)
CONFIG_CTL (r/w)
IO_ADR (r/w)
IO_DATA (r/w)
IO_CTL (r/w)
SRC_ADR (r/w)
DEST_ADR (r/w)
DMA_CTL (r/w)
INT_CTL (r/w)
DRAM_BASE (r/w)
MMIO_BASE (r/w)
PRELIMINARY SPECIFICATION
31
31
31
31
31
31
27
27
27
27
27
27
T
D
RMA Received Master Abort
RTA Received Target Abort
23
23
23
23
23
23
RMD (Read Multiple Disable)
Error: Duplicate io_cycle or config_cycle
TTE Target Timer Expired
• writing to SDRAM_BASE moves the origin of any
• writing to MMIO_BASE moves devices around, and
• writing to both registers in sequence requires a
SDRAM Base Address
MMIO Base Address
DN
executing DSPCPU program, which will cause it to
fail
moves MMIO_BASE and SDRAM_BASE around
delay, due to the implementation. It is recommended
to space such writes far apart, or iterate until the first
register written to reads back with the new value
before writing the second one.
Error: Duplicate dma_cycle
19
19
19
19
19
19
SR (PCI Set Reset)
Destination Address
Configuration Data
PCI Address
CR (PCI Clear Reset)
Source Address
I/O Address
PCI Data
I/O Data
IE (ICP DMA Enable)
PCI-to-SDRAM
HE (Host Enable)
Reserved
15
15
15
15
15
15
dma_cycle
TL
11
RW (Read/Write)
RW (Read/Write)
11
11
11
11
11
Philips Semiconductors
Done
io_cycle
IS
config_cycle
Busy
BO (Burst Mode Off)
SE (Byte Swap Enable)
FN
Done
Busy
7
7
7
7
7
7
Done
IE
Busy
IntE
RN
Done
Busy
P
P
3
3
3
3
3
3
INT
BE
BE
T
T
0
BN
M
M
0
0
0
0
0
0
0