SAA7115HLBE NXP Semiconductors, SAA7115HLBE Datasheet - Page 205

• Manufacturer Part Number: SAA7115HLBE
• Description: Video ICs ADV DGTL VIDEO DECODR
• Manufacturer: NXP Semiconductors

Specifications of SAA7115HLBE

• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 70 C
• Package / Case: SOT-407
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Number Of Channels: 2
• Resolution: 8 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: SAA7115HL/V1,557 SAF7115HLBE

Philips Semiconductors
13.2.2
In a system where PNX1300 serves as the host CPU, the
system boot block performs an autonomous boot proce-
dure. For an autonomous boot, the system boot block
reads all the information described in
“Boot Procedure Common to Both Autonomous and
Host-Assisted Bootstrap,”
tonomous boot bit is set—continues reading information
from the EEPROM. After this part of the system boot pro-
cedure is done, the DSPCPU starts executing. See
Table
The DSPCPU bootstrap program byte count encodes the
number of bytes of DSPCPU program code contained in
the EEPROM(s). This 11-bit unsigned byte count can en-
code up to 2048 bytes, which is also the maximum
amount of EEPROM storage supported. The actual
amount of EEPROM available for the DSPCPU boot-
strap program is limited to 2000 bytes. Other information
consumes 47 bytes, and the DSPCPU code must be an
integral number of 32-bit words.
Four pairs of 32-bit MMIO-register addresses and values
follow the bootstrap program byte count. Each address
tells the boot block where in the 32-bit DSPCPU address
space to store the corresponding 32-bit value.
The
MMIO_BASE sets the base address of the 2-MB MMIO-
register address aperture within the DSPCPU 32-bit ad-
dress space. All MMIO registers are addressed using an
offset that is relative to the value of MMIO_BASE. For
this pair, the address is required to be 0xEFF00400 be-
cause that is the default MMIO_BASE enforced when
PNX1300 is reset. The new value for MMIO_BASE is en-
coded in the corresponding value.
The DRAM_BASE address/value pair determine the
base address of the SDRAM address aperture within the
32-bit DSPCPU address space. The address must be
equal to 0x100000 plus the new value of MMIO_BASE
set previously in the boot procedure. The DRAM_BASE
value must be naturally aligned given the rounded DRAM
aperture size, i.e. a 6 MB DRAM aperture should start on
a 8 MB address multiple.
The DRAM_LIMIT address/value pair determine the ex-
tent of the SDRAM address aperture. The address must
be equal to 0x100004 plus the new value of
MMIO_BASE set previously in the boot procedure. The
value in DRAM_LIMIT should be 1 higher than the ad-
dress of the last valid byte of SDRAM memory, and must
be a 64 KB multiple.
The DRAM_CACHEABLE_LIMIT address/value pair de-
termine the extent of the cacheable aperture of the
SDRAM address space. The address must be equal to
0x100008 plus the value of MMIO_BASE set previously
in the boot procedure. The cacheable aperture always
begins at the address value in DRAM_BASE; the value
in DRAM_CACHEABLE_LIMIT is one higher than the
address of the last byte of cacheable SDRAM memory,
and must be a 64 KB multiple. It is safe to initially set the
value
13-4.
first
of
Initial DSPCPU Program Load for
Autonomous Bootstrap
pair
DRAM_CACHEABLE_LIMIT
initializes
and then—because the au-
the
MMIO_BASE.
Section 13.2.1,
equal
The
to
Table 13-4. Information Loaded During Second Part
of Bootstrapping Procedure for Autonomous Boot
DRAM_LIMIT. The RTOS can, if desired, change the val-
ue later.
The next 32-bit value in boot EEPROM memory is a copy
of the DRAM_BASE value encoded previously. The sys-
tem boot hardware loads the DSPCPU bootstrap pro-
gram into SDRAM starting at DRAM_BASE.
The bytes of the DSPCPU bootstrap program follow the
copy of the SDRAM_BASE value. The bootstrap pro-
gram can consist of up to 500 32-bit words of DSPCPU
PRELIMINARY SPECIFICATION
DSPCPU bootstrap pro-
gram byte count n
MMIO_BASE address
MMIO_BASE value
DRAM_BASE address
DRAM_BASE value
DRAM_LIMIT address
DRAM_LIMIT value
DRAM_CACHEABLE_
LIMIT address
DRAM_CACHEABLE_
LIMIT value
DRAM_BASE value
SDRAM code word 0
SDRAM code word 1
SDRAM code word n/4
Information
.
.
.
32-bits MMIO_BASE + 0x100004
32-bits First 32-bit word of initial
32 bits Value must be
32 bits Value is simply written to
32 bits MMIO_BASE + 0x100000
32-bits Value is simply written to
32-bits Value is simply written to
32-bits MMIO_BASE + 0x100008
32-bits Value is simply written to
32-bits Copy of the DRAM_BASE;
32-bits Second 32-bit word of ini-
32 bits Last 32-bit word of initial
11 bits up to 500 32-bit words
Size
.
.
.
(2048 bytes less 47 header
bytes)
0xEFF00400
0xEFF00400 to determine
new base address of 2-MB
MMIO register aperture
within 32-bit DSPCPU
address space
DRAM_BASE to determine
base address of SDRAM
aperture within 32-bit
DSPCPU address space
DRAM_LIMIT to deter-
mine limit address of
SDRAM aperture within
32-bit DSPCPU address
space
DRAM_CACHEABLE_LIM
IT to determine limit
address of cacheable part
of SDRAM aperture within
32-bit DSPCPU address
space
must be equal to value
specified above
DSPCPU bootstrap pro-
gram
tial DSPCPU bootstrap
program
DSPCPU bootstrap pro-
gram
Interpretation
System Boot
.
.
.
13-5