SAA7115HLBE NXP Semiconductors, SAA7115HLBE Datasheet - Page 159

• Manufacturer Part Number: SAA7115HLBE
• Description: Video ICs ADV DGTL VIDEO DECODR
• Manufacturer: NXP Semiconductors

Specifications of SAA7115HLBE

• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 70 C
• Package / Case: SOT-407
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Number Of Channels: 2
• Resolution: 8 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: SAA7115HL/V1,557 SAF7115HLBE

Philips Semiconductors
Figure 10-3. Bi-phase mark data transmission
the settings of the DDS (see
Programming”).
Figure 10-3
data value “10011000”, as well as the transmission for-
mat of the 3 pre-ambles. Note that each pre-amble al-
ways starts with a rising edge. This is made possible
thanks to the presence of the parity bit, which always
guarantees an even number of ‘1’ bits in each sub-frame.
10.6
The parity bit, or P bit in
SPDO hardware. The P bit value should be set such that
bit cells 4 to 31 inclusive contain an even number of ‘1’s
(and hence even number of ‘0’s). The P bit is bi-phase
mark encoded using the same method as for all other
bits.
10.7
The DSPCPU software must prepare a memory data
structure that instructs the SPDO hardware to generate
correct IEC-958 blocks. This data structure consists of
32-bit words with the following content:
Table 10-2. SPDIF sub-frame descriptor word
31 (MSB) this bit must be a ‘0’ for future compatibility
30..4
3..0
(LSB)
bits
W
M
B
IEC-958 PARITY
IEC-958 MEMORY DATA FORMAT
“1”
Data value for bits 4..30 of the subframe, exactly
as they are to be transmitted. Hardware will per-
form the bi-phase mark encoding and parity gen-
eration.
0000 - generate a B preamble
0001 - generate a M preamble
0010 - generate a W preamble
0011 .. 1111 reserved for future
illustrates the transmission format of 8-bit
“0”
“0”
Figure
“1”
Section 10.8, “Sample Rate
definition
UI
cell
“1”
10-2, is computed by the
bi-phase mark violation
bi-phase mark violation
bi-phase mark violation
“0”
“0”
“0”
The data structure for a block consists of 384 of these 32-
bit descriptor words, one for each subframe of the block,
with the correct B, M, W values. All data content, includ-
ing the U, C and V flag are fully under control of the soft-
ware that builds each block.
A DMA buffer handed to the hardware is required to be a
multiple of 64 bytes in length. It can contain 1 or more
complete blocks, or a block may straddle DMA buffer
boundaries. The 64-byte length will result in DMA buffers
that contain a multiple of 16 sub-frames.
Note that the descriptor structure is a 32-bit word memo-
ry data structure, and is hence subject to processor en-
dian-ness. To allow software to be efficient in both little-
endian and big-endian operation, the SPDO block
SPDO_CTL
‘LITTLE_ENDIAN’. The SPDO block performs byte
swapping when loading the SPDIF descriptors as fol-
lows.
• If LITTLE_ENDIAN = 1, 32-bit words at address ‘a’
• If LITTLE_ENDIAN = 0, 32-bit words at address ‘a’
10.8
In he SPDO unit, the frame rate always equals f
sample rate of embedded audio. This relation holds for
PCM as well as for Dolby AC-3 and MPEG encoded au-
dio. Each frame consists of 128 Unit Intervals (UI’s). The
length of a UI is determined by the frequency setting of
the DDS (Direct Digital Synthesizer) in the SPDO block.
The DDS can be programmed to emit frequencies from
approx. 1 Hz to 80 MHz in steps of approx. 0.3 Hz, with
a jitter of approx. 750 psec (at DSPCPU frequency of 143
MHz, see equations below).
Programming is accomplished through the FREQUEN-
CY MMIO register: the relation between FREQUENCY
register value, DSPCPU clock value and synthesized fre-
quency is:
Putting equation 1 and 2 above together yields the for-
mula for setting FREQUENCY to accomplish a given
sample rate:
The DDS synthesizer maximum jitter can be computed
as follows:
PRELIMINARY SPECIFICATION
will be assembled from bytes (a+3,a+2,a+1,a), with
the byte at ‘a+3’ containing the MSB’s and the byte at
‘a’ the LSB’s.
will be assembled from bytes (a,a+1,a+2,a+3), with
the byte at ‘a’ containing the MSB’s and the byte at
‘a+3’ the LSB’s.
f
FREQUENCY
FREQUENCY
s
=
SAMPLE RATE PROGRAMMING
(
--------------- -
f
128
DDS
register
)
=
=
2
2
has
31
31
+
+
---------------------------- -
9 f
---------------------------- -
9 f
f
DDS
⋅
an
⋅
f
s
DSPCPU
DSPCPU
⋅
2
⋅
endian-ness
39
2
32
SPDIF Out
Eq. 1
Eq. 2
s
, the
10-3
bit